Right. Vsync stay high until retrace, at which point it drops to low (once per frame). Hsync is a little bit more confusing for me. This changes once per scanline?
I think my best bet is to provide a clock input to the FPGA of 7.8336MHz. This would be the series of operations, greatly simplified:
1.) At start up, wait for a low on the Vsync signal, indicating a new frame.
2.) Once per clock cycle, I'm not sure on the rising or falling edge, write the value of the video signal to the correct position (a simple counter would suffice) in the frame buffer.
3.) When the Vsync signal goes low, write the buffer to the LCD.
4.) Go to #2.
I think my best bet is to provide a clock input to the FPGA of 7.8336MHz. This would be the series of operations, greatly simplified:
1.) At start up, wait for a low on the Vsync signal, indicating a new frame.
2.) Once per clock cycle, I'm not sure on the rising or falling edge, write the value of the video signal to the correct position (a simple counter would suffice) in the frame buffer.
3.) When the Vsync signal goes low, write the buffer to the LCD.
4.) Go to #2.