Hokay... the PowerMac 6100/60 has a 30MHz crystal oscillator onboard, which means it's suppling the bus clock. Page 488 of the PowerPC 601 Users' Guide (http://stuff.mit.edu/afs/sipb/contrib/doc/specs/ic/cpu/powerpc/mpc601.pdf) makes it look like BCLK_EN controls the core/bus ratio by oscillating appropriately. In particular, it looks like tying it to ground would cause the CPU clock to equal the bus clock.

Let's talk about examples in a 6100/60, for concreteness' sake...

Would the chip be smart enough to run at 30MHz if BCLK_EN was tied to ground, despite the presence of the 60MHz and 120MHz inputs? In effect, there'd be a wait-state after every instruction.

Or, would this cause the CPU to think that the bus speed was actually 60MHz, in disagreement with reality? Would it be necessary to tie the 60Mhz output of the clock-chip to the 2X_PCLK and the 30MHz to PCLK_EN, in addition to tying BCLK_EN to ground?

I *really* wish I had a fast, dual- or tri-trace scope... :-(