If I lay my hands on one, I'll try to make sure you get a chance to poke at it.
How does one avoid collisions with CPU activity while flashing the FPGA? (On the PDS bus)
Intriguing - a possible method for new FPGA-based expansion devices which saves a little board space and component expense?
How does one avoid collisions with CPU activity while flashing the FPGA? (On the PDS bus)