The CPU writes to the FPGA to configure it thru the same buss it sends video after the FPGA is running, so there is no buss conflict. I think Lapis embedded the config within the driver, instead of using an EPROM, so the FPGA data is easily extracted and hacked by editing the driver file. Xilinx chips are wonderful toys. Beck-Tech made video output adapters that snapped into the security slot of 128 / 512 / Plusses, and I believe Steve Beck continued that after he started Lapis.