"johnklos", _You can not make it work without the help of PLL chip in any way_! (PLL stands for Phase Locked Loop, check Google or Wiki how it works, in caseYou don't know.)In all Quadras + IIVx this PLL works as Frequency doubler. That means, you put 12.5MHz in and out comes 25MHz. You put 20MHz in -> out comes 40MHz.

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I'm sorry, but how can you tell me that I can not make it work when I've been running at least one of my Quadra 605s at 40 MHz this way for a decade? That doesn't make any sense.

If the manufacturer says what we should use, it would be good engineering practice to follow his recommendations. In our case we all should be using DW80 version, not even DW70!
Running 35 MHz part (DW70) @ 40 MHz is already 5 MHz too much, but running 25 MHz part at that frequency is living on the edge.

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If that were true, nobody would overclock since overclocking is almost always running parts faster than what the manufacturer says.

We're talking about a simple PLL clock driver, not a multiple-million-transistor device like a CPU. Also, the implementations and specifications are identical for both with the only exceptions being a recommended change in the anti-jitter resistor for applications below 40 MHz (20 MHz CPU) and the guaranteed minimum working frequency:

http://www.mac68k.org/files/MC88916.pdf

http://www.mac68k.org/files/MC88920.pdf

The added oscillator's output simply goes to pin 8 of the MC88920 which is disconnected because of the removal of R93. How is that not working with a PLL when we're precisely working with the MC88920?