Datasheet for the M5M27C101JK is here:http://www.io.com/~trag/DataSheet

I thought I had it on my archive drive. I have a last modified date of 2003 on it. I think we're covering some of the same ground which Gamba and I covered back in 2003 when we worked on the IIci ROM together. New ground too, since your ideas for modifying the ROM are very cool.

Click to expand...

I saw in an older thread that you worked with Gamba on the IIfx also. Back around that same time period, I was trying to figure out a way to address more RAM per slot on the IIfx MoBo. After Dr. Bob went bonkers about how horrific a certain pizzabox memory hack was in terms of noise and timing, I figured out another possible, hopefully far less objectionable, approach.

IIRC the IIfx RAM is multiplexed and there are, for the vast majority of these machines, unused parity checking lines. My notion was that these lines could be rework jumpered/hijacked at the memory controller or CPU, becoming additional lines for addressing much more memory on an entirely new RAM card design. I know Gamba had a IIfx RAM SIMM layout for the maximum "normally" addressable memory ceiling. However, I was thinking it might be possible to add a few more bits of addressing through a parity line rework/hijack hack. I don't recall much offhand about the IIfx memory mapping, but the additional memory should, at the very least, be addressable as a RAMdisk, configured as Virtual Memory, and accessed at the same speed as normal system memory.

It's been a long time since I've toyed with the idea, so I thought I'd bounce it off you before hittin' the books again. }