One thing to look out for when fitting a ROM/cache module in a machine which already has ROM is that the module does not disable the on-board ROM.
Apple has a pretty clever scheme it uses in some machines. The CE_ (chip enable; active low) pins of the on-board (logic board) ROMs are tied low through a large resistance. The CE_ pins also connect to a pin in the ROM slot. In order to disable the logic board ROMs, all the ROM module must do is connect the logic-board-ROM-CE_ pin to +5 (or +3.3V for later machines) with less resistance than was used to ground the pins. This causes CE_ on the logic board ROM to go high and the logic board ROM chips are disabled.
I do not know if Apple used this particular scheme on the machine you're looking at, but you should check, as it would prevent any ROM/Cache module from working in your machine, no matter what you do to the ROM on the module.
Typically, you won't be able to find pinouts or even model numbers for the ROMs. However, if you look up equivalent capacity Flash or EEPROM in the same package, the pinout will be the same as they follow JEDEC standards, which will allow you to identify the CE_ pins on the ROM chips.
Also, the cache and ROM chips are likely to share address and data lines on the module. I think some of the earlier discussion was puzzled by this. Until you get to PPCs with lookaside or backside caches, the cache is using the same address and data lines as the main busses and so they're going to share those resources. It's possible that the address lines might be decoded through different hardware and so the address lines not shared, but the data lines are almost certain to be shared as a bus by the cache and ROM.
Apple has a pretty clever scheme it uses in some machines. The CE_ (chip enable; active low) pins of the on-board (logic board) ROMs are tied low through a large resistance. The CE_ pins also connect to a pin in the ROM slot. In order to disable the logic board ROMs, all the ROM module must do is connect the logic-board-ROM-CE_ pin to +5 (or +3.3V for later machines) with less resistance than was used to ground the pins. This causes CE_ on the logic board ROM to go high and the logic board ROM chips are disabled.
I do not know if Apple used this particular scheme on the machine you're looking at, but you should check, as it would prevent any ROM/Cache module from working in your machine, no matter what you do to the ROM on the module.
Typically, you won't be able to find pinouts or even model numbers for the ROMs. However, if you look up equivalent capacity Flash or EEPROM in the same package, the pinout will be the same as they follow JEDEC standards, which will allow you to identify the CE_ pins on the ROM chips.
Also, the cache and ROM chips are likely to share address and data lines on the module. I think some of the earlier discussion was puzzled by this. Until you get to PPCs with lookaside or backside caches, the cache is using the same address and data lines as the main busses and so they're going to share those resources. It's possible that the address lines might be decoded through different hardware and so the address lines not shared, but the data lines are almost certain to be shared as a bus by the cache and ROM.