In theory, it isn't. There's a clever IDSEL scheme which is still kind of at the slot signal level, but it just involves tieing one of the slot signals to one of the addressing lines. So no unique signal, just an extra pin to let a slot listen to an address line through a different wire.
However, the interrupts on Apple machines are slot unique. There are four interrupts per slot in the PCI spec. and they can be shared from slot to slot. The typical recommendation is to rotate the available interrupts amongst the four signals pins from one slot to another. So, CPU_INT(1) connects to INTA in slot 1 and INTB in slot 2 and INTC in slot 3, etc. Similarly for CPU_INT(2).
But that's not what Apple did. Apple ties all four interrupt pins together in each slot and gives each slot its very own unique interrupt signal line. In the X500 family, that's a wire back to Grand Central per PCI slot. In the 6500 that's a wire to Heathrow per PCI slot.
I guess in non-Apple systems there's some method to poll the interrupts when you run the IDSEL thing to tell which slots are using which interrupts, but Apple's machines don't have that intelligence.
And yes, if one uses a PCI-PCI bridge (expansion chassis) all of the downstream slots end up using the interrupt of the host slot, but that's built into the PCI spec. and expected.
Additionally, bus mastering requires a bus arbitration scheme. In order to arbitrate who has control of the bus, there must be unique GNT and REQ wires to each slot. And yes, on Apple machines, every single PCI slot is a bus mastering slot. I see the term get thrown around a lot (especially on xlr8yourmac.com) talking about this or that slot being a mastering slot, but that's a red herring. They're all capable of bus mastering. They all have GNT and REQ signals.
On the x500 machines, PCI bus arbitration is handled by a little PLD separate from Bandit. It's something like 341S0088. It's a little 20 pin thing, IIRC. On the 6500 it's probably all built into PSX+.
When one uses a PCI-PCI Bridge (expansion chassis) the slot arbitration for downstream slots is handled by the bridge. That's part of what a PCI-PCI Bridge does.
That's irony.
