maximum stable bus speed was also connected to what cpu I drop in there even when settings remained the same.
Didnt know of the CLOCKID pins back then and dont know if my MACH Carrier sets them but i guess so. Question is can the used ZIF module mess with those CLOCKID settigns as not all CPUs seemed to work at 62mhz? for some i had indeed go down to 45mhz to get them to boot at all.

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It may also be the case that the PFD in the PLL of some CPUs does not support speeds above 50 MHz. The PFD is the component in the PLL which compares the incoming reference clock speed to a feedback signal from the CPU clock signal. There are various dividers in place so that the comparison makes sense. The PLL is the set of components which are used to set the clock multiplier and keeps the internal clock system of the chip reasonably steady.

This should be fairly easy to check by reading the datasheet, but they may not have provided that level of detail about the internal PLL.