So are the PDS pass-through slots in series? http://www.biwa.ne.jp/~shamada/fullmac/se30_minitowerEng.html indicates 6 addresses. Maybe the PAL is tapping into the PDS and switching-off between sending instructions to the IIci cache slot and passing them through to the rest of the PDS chain?

My point is, I am guessing the SE/30 PDS slot has more going on than just routing lines to the CPU, and that's why to get it to a state the PowerCache can handle, it needs to involve some logic.