But Even though this isnt analog or RF, and its digital, at breakneck speeds circuit lengths still become an issue. Even though its only 1s and 0s, The transition between 1 to 0, and 0 to 1 still fall into the "analog" domain. And CMOS/TTL have their own properties on which either state is recognized. So the less time the transition is spent in the undefined gray area, the better off you are. Therefore, if the rise-time or fall-time is grossly out the window, strange things happen. Now granted, the discussion about socketed/non-socketed CPUs at the SE/30 clock speeds, it doesnt matter... The clock is too slow even for the longest mess of a trainwreck wire to even matter. So my argument is moot.
But hypothetically when you start operating at clock speeds at the several hundred Mhz, those "wires" and their lengths and parasitic capacitive loading start coming into play, If the circuit trace or pin is too capacitive loaded it could cause race conditions in a parallel signal getting from A to B. And at even higher speeds, parasitic inductance start putting glitches on the line. Thats even worse....

Which is why if you look at modern motherboards, speed critical circuits are meandered to have equal lengths between A and B across all data lines.

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