Ah, thank you. That's a great technical note. I had a vague memory of having read about refresh issues, but I (wrongly) thought that it only applied to the II/IIx PAL SIMM subject.
Still, the 2-chip SIMM limitation is not so bad. It only applies to the Plus and earlier, the SE, Classic and the II and IIx.. I guess pre-Plus don't have SIMM sockets, but the upgrades might have similar issues.
So, if you have 1M of addresses on a memory chip, and it uses 512 refresh, that implies 9 row address bits? Refresh is by rows, yes? So the early machines expect their 1M RAM to be organized as 9 X 11 (row address bits X column address bits)?
Hmmm. Seems the above is wrong, but I haven't puzzled it out yet. I'm looking at a datasheet for the Hitachi HM511000 which has ten address pins and uses 512 refresh cycles. It specifies A0 - A8 as refresh address input.
I can only guess that the multiplexed address rows for data don't correspond to the refresh rows, in some manner. I thought that they always did. To get 1M addresses, this RAM must be using 10 X 10 addressing, because there are only 10 address pins available. Can't use 9 X 11 when there's no number 11 (or A10). 10 X 10 addressing implies 1024 rows and 1024 columns. Yet only 512 rows are used for refresh. Perhaps it refreshes two rows at a time? I'm going to post this while I continue looking. Feel free to jump in.
I'm also ignorant of how CAS_ Before RAS_ Refresh works. That doesn't appear to require a Row Address at all according to the timing diagrams. Does that refresh the whole chip (all the rows) and so make the memory unavailable for a long block of time, with a corresponding long block of availability until the next block refresh? Or is there an internal address counter which assigns a row address on a CAS_ Before RAS_?
hm511000.pdf
MSM514400D.pdf