The reason 2/3 chip SIMMs usually don't work is because the 4Mbit memory ICs they use usually require a 1024 row refresh cycle. The Plus, SE, and Classic only supply a 512 cycle refresh. (Page 21)
If there are are indeed 2/3 chip SIMMs that work they probably do so because the ICs used on those particular SIMMs incorporates a 512 cycle refresh for backwards compatibility. This problem has come up before: the very common 4164 DRAM used during the 8-bit era came in both "native" 256 cycle and backwards-compatible-with-4116's 128 cycle versions. (There was a lot of demand for this because the very popular Z-80 CPU included a 7 bit memory refresh counter built-in; using the 256 count ICs required adding additional logic. But it doesn't just affect Z-80 machines; if you're replacing RAM in an Apple IIe I believe it's an issue with them too... in fact, the 7 bit counter chips seem to be the most common to this day.) If you have a 2 chip SIMM that works in a Plus it might be worth a laugh to try to look up the specific datasheet for the RAMs on it and see what it has to say about refresh cycles.
If there are are indeed 2/3 chip SIMMs that work they probably do so because the ICs used on those particular SIMMs incorporates a 512 cycle refresh for backwards compatibility. This problem has come up before: the very common 4164 DRAM used during the 8-bit era came in both "native" 256 cycle and backwards-compatible-with-4116's 128 cycle versions. (There was a lot of demand for this because the very popular Z-80 CPU included a 7 bit memory refresh counter built-in; using the 256 count ICs required adding additional logic. But it doesn't just affect Z-80 machines; if you're replacing RAM in an Apple IIe I believe it's an issue with them too... in fact, the 7 bit counter chips seem to be the most common to this day.) If you have a 2 chip SIMM that works in a Plus it might be worth a laugh to try to look up the specific datasheet for the RAMs on it and see what it has to say about refresh cycles.