YaccDesc

YaccDesc.Text Thu, Mar 16, 1989 11 :30 PM The YACC is a r meg machine ~:Ji th memory management that al 1m'ils mapping of the memory into 1 kilobyte pages. There are 8 video planes which are 640*480 pi:-~els in size. This is 37.5K of ram per plane; the 1K resolution of the pages force an a 11 ocat ion of 38K for each p1ane. The Video DMA system uses physica1 addresses 19 to 17 for the selection of the 8 planes, thus forcing the division of the physical 1 meg of memory into 8 128K partitions. There is a i6 bit register that is loaded with a physical address that points to the start of the frame buffer in each of the 8 p1anes. The Sound subsystem makes a 11 accesses f ram partition 0, which has addresses 17, 18, and 19 = 0. It also has a 16 bit register ~'ilhich points to the start of the sound buffer. The system vlill fetch a 16 bit value·at the start of video scan line (15.734 KHz horizontal scan rate), of which the lovJ 10 bits are used as input to a PWM circuit. The PWM circuit divides the 1ine into 585 cycles; a value of 585 or higher ~-vill turn on the sound for the entire line whi 1e a value of 0 wi 11 tur·n off the sound for the i ine. The Sound DMA system will continue to fetch successive words of data untii a ~'4ord is read that ha·:; bit 15 = 1, whereupon the circuit ~'iliil reset the starting address to the intial vai ue in the 16 bit register. _ The floppy disk Pl4M circuit for speed control is two 8 bit registers/counters that are written in parallel. When 16 bits are ~~ritten, the low 8 bits are loaded into a F'WM_Lm•J register and the high 8 bits are iaoded into a Pl4M_High register. The cirrni t provides Pulse Width Modulation and Pui se Frequency -Modulation. Each register is fed into a counter that increments at an BMHz rate until it reachs 255, whereupon it ha 1t and re 1oad i tse l f • The other regi stericounter is enab 1ed and it fol i ovJS an identical process. The number of time::; that both counters increment i·; proportional to the square-wave frequency that is produced • ~Ji th a sum of counter increments equal to 256, a square ~'ilave of frequency 3i.25Khz is produced {1000/ \256* ( 1000000/BMHz ! ) ) • The va1 ue in the PviM_Low register/counter divided by 256 is the proportion of the square ~·Jave that will be 1ow and the value of Pi~M_High divided by 256 is the proportion of time that wi 1i square wave ~:.Ji i1 be high. The memory management hard~...;are consists . of 2K ;{ 16 of readiwrite registers. 8 megabytes can be mapped but on 1y 1 megabyte can be mapped at any one time. Any 2 accesses that has the low 19 bits the same and the high 3 bi ts are different vJili cause a memory translation error. To address 1 meg, bits 19-10 are provided by the MMU and 9-1 come directly from the address. The high 3 bits (22-20) are used by the MMU. To write the MMU, the 16 bits are mapped as follows: Bit 15 Bit 14 Bit 13 Bi ts 12 :03 Bits 02 : 00 Referenced bit , = 1 if page has been referenced • - Modified bit, = l if …