DMU Disk Controller Register Operation

-------- CONFIDENTIAL ----------------------------------- CONFIDENTIAL -------- * DMU Disk Controller Register Operation * and * State Sequencing * Burrell Smith 10 October 1984 Copyright Apple Computer -------- CONFIDENTIAL ----------------------------------- CONFIDENTIAL -------- OVERVIEW The DMU has two DMA channels, Channel 0, which supports an internal 20 Megabyte Nisha Winchester disk drive, and Channel 1, which supports a general purpose high speed serial DMA link. Each channel has enough bandwidth so that the internal Winchester and another peripheral of slightly less than 8 Mhz transfer rate each appear to have concurrent access to the DMU RAM. Double these values when calculating the peak transfer rates available for a one Megabyte memory configuration, since the memory data bus in systems employing the DMU support a 32 bit memory bus. The Winchester controller (Channel 0) supports consecutive sector DMA for reads, the common case, without requiring CPU intervention. Writes, which must be performed at two-to-one interleave because of the Winchester's long recovery time following a write (this prohibits reading the header on the following sector) may only be written a sector at a time •. This requires the internal AMU registers to be reloaded every 1.2 rns for writes (design change pending to eliminate this and allow sector blocks for writes). The Winchester controller also supports variable-size sectors at single byte increments, up to just under 4K bytes in size, and up to 64 sectors per track. The General Purpose DMA channel transfers data in a block of up to 32K bytes per transfer, and restricts the transfer to a contiguous block. The General Purpose channel supports laser printing, and other external peripherals. This document presents detailed information only on the Winchester Disk Controller, Channel 0. The DMA steals cycles from the CPU for each transfer. Dedicated bandwidth assigned to the CPU guarantees a minimum of approximately 25% of full bandwidth for the 68000, eliminating processor lockout because of a faulty peripheral. Although almost all the registers needed for a DMA transaction reside in the DMU, two important registers do not. These are the DMA Memory Pointers, which point to a physical location in RAM as the source or destination for DMA 10 October 198~ DMU Disk Controller Page 2 transfer. Following each transfer, the Memory Pointers increment by one 16-bit word. In 32 bit configurations, the Memory Pointers increment by two 16-bit words. Consult the Turbo Memory Map document for details about how to address these registers. In normal operation, the Memory Pointers will be changed only at the beginning of a transfer. They are write only registers. CHANNEL 0 REGISTERS 1. Register Addressing The DMU appears as two word locations: the Address Register and the Data Register. The Address Register selects one of the Data Registers for reading or writing. All registers are read-only or write-only, and the direc…