VIA Cell Preliminary Specification Nov1989

VIA Cell Preliminary Specification VIA Table of Contents 1.0 Overview ............................................................................................ 4 2.0 Guidelines for using the VIA Cell within a larger chip ................................ , ....... 4 3.0 Global Reset (Reset_) .............................................................................. 4 4.0 Internal C783K Clock ............................................................................. 5 5.0 VIA Cell Bus Interface ............................................................................ 5 5.I VIA Cell DSACK_ ..................................................................... 5 5.2 VIA Cell Chip Select (CS) ........ , .................................................... 5 5.3 Read/Write (RW) ........................................................................ 5 5.4 Data Bus (Din[7:0] and Dount[7:0]) .................................................. 5 5.5 RegSel[3:0] Register Selects ............................·............·.................. 5 ' 5.6 Interrupt Request (IRQ_) ............................................................... 6 . 6.0 Peripheral Data Ports (Ports A and B) ..................................... , ....... : ............. 6 6.1 Peripheral Data Port A (PA7-PA0) ...................•............................... 6 6.2 Peripheral Data: Port A Control Lines (CAI, CA2) .....•.......... :.~ .............. 7 6.3 .. Peripheral Data Port B {PB7'"PBO) .............. ; ............................ ; ....... 7 6.4 . Peripheral Data Port B Control Lines (CB I, CB2) ............................... ·.. 7 7.0 Timer I - Operation .................................... ; .............................................. 7 7. I Timer I -· One-Shot Mode .............................................................. 8 7.2 Timer I - Free-Run Mode .............................................................. 8 8.0 Timer 2 - Oi)eration ................................................. , .............................. 9 8.I Timer 2 - One-Shot Mode ...............................................•............... 9. 8.2 Timer 2 - Pulse Counting Mode .............. ;........................................ 9 9.0 Shift RegisterOperation ...................... , ............ : ....................................... 9 9.I Shift Register Disabled (000) .................................. ~ ...................... 10 9.2 Shift In - External CBI Clock Control (011) ....................................... 10 9.3 Shift Out- External CBl Clock Control (111) .............................. .-...... 10 IO.O Interrupt Operation ........................................................ : .... : .................. 11 I 1.0 Testing the VIA Cell .................................................................. ~· ........... 12 Page 2 of 26 re Technology VIA Cell Preliminary Specification Table of Figures Figure 1 Simplified VIA Cell Block Diagr…