Livonia ERS 1.4.2

MCP BASED DMA SERIAL CARD ("Livonia") REV 1.4.2 (PVT PHASE) Mark Devon Networking and Communications 11/16/89 TABLE OF CONTENTS 1.1 System Overview 2.1 Processor 2.2 ROM 2.3 RAM 2.4 NuBus Interface 2.5 SCC Interface 3.0 Hardware Description Details 3.1 Address Map 3.2 NuBus Address Space 3.3 Timer 3.4 Reset 3.5 Interrupts 3.6 SCC Access 3.7 Serial I/O Signals 3.8 Serial Status Register 3.9 Configuration 3.10 Connector 4.0 DMA chip and registers 4.1 DMA Interface to MCP Local Bus 4.2 Access to DMA Registers by 68000 4.3 MC68450 DMA to 8530 SCC Interface 5.0 Cabling 6.0 Performance 7.0 Mechanical/Environmental 1.1.2 System Overview The "Livonia" board is a card with a full NuBus Master/Slave interface with a 68000 processor , 1/2 Mbyte of RAM (expandable to 2.5Mb), two SCC's and one Mc68450 DMA chip (4 channels) on board. It is based on Gary Martens' MCP Nubus interface card. The card provides four active ports, two of which can be run at speeds greater than 19.2kbit/s. These two high speed serial ports may be configured as V.35 ports for driving 56kb/s leased line DDS (modem-like) devices, or as RS-232 ports. The configuration choice is made by the type of connecting cable used. The 68000 can access any device on the NuBus. The DMA, EPROM, SCC's, local RAM and DTR/DSR registers and all may be accessed via Nubus. Accesses by the DMA to the Nubus are NOT supported. 2.1 Processor The I/O Processor utilizes a 10MHz 68000 processor with no wait states for accesses to onboard RAM. The 10MHz clock is derived from the 10MHz NuBus clock. All access by the 68000 are implemented by a 16-bit data bus with byte mode also supported. Accesses to the SCCs are done on a byte wide basis on D0-7 (odd addresses). Accesses to the DMA may be either byte or word mode. 2.2 ROM The 16-bit wide ROM is implemented with two 256K bit ROMS yielding a 64K byte ROM space. The ROM serves as "power-up" code for the 68000, a place for user firmware, and it also stores the NuBus ID data for the card. The ROM inserts one wait state when accessed by the onboard 68000. To the NuBus interface, ROM appears as a full 32-bit wide device, supporting 8-bit, 16-bit and 32-bit bus reads. 2.3 RAM The card contains 1/2 Mbyte of 16-bit wide dynamic RAM, with sockets available for a second 1/2 Mbyte (all ZIP chips). RAM is accessed by the 68000, NuBus, and the two DMA Chips (MC68450). When any device on the card is accessed via NuBus, the 68000 is locked out from all accesses. RAM starts at location 000000, with the default 1/2 Mbyte of RAM, the last RAM address is 07FFFF. When the 68000 accesses onboard RAM, no wait states are inserted. When the 68450 DMA chip accesses RAM, one wait state is inserted on write cycles, zero wait states inserted on read cycles (this is an anomaly in the DMA chip itself). Provision is made for future 4 Mbit DRAM ZIP chips (Qty. 4) which, when combined with the 1/2 Mbyte already present would give total of 2.5 Mbyte of RAM on the card. Pin 10 of the 1Mb …