TFB Specification

TFB SPECIFICATION Frame buffer specification for 1 February 1986. comments and questions are encouraged, direct them to Toby Farrand at MIS 22Y x2524. TFB Specification Apple Confidential UPDATES TO THE SPECIFICATION The following is a list of changes made to the frame buffer specification for the 28 June 1985 version of the document. 123456789- Support for the planar color model has been dropped from section 1.3. The frame buffer memory map has been updated in section 2.0. Many of the control register definitions have changed in section 3.0. Several pin definitions have changed in section 4.0. Test mode operation has changed, and is explained in section 4.3. Planar mode accesses have been eliminated. Data transfer cycles are changed in section 5.2. Appendix A has been added to suggest possible configurations using the TFB. Timing information has been added in Appendix B. The following is a list of changes made to the frame buffer specification for the 1 February 1986 version of the document. These changes apply only to the 1.1 version of the TFB. 12345678911 10 - Support for variable depth color has been added to the chip. Support for multiplexed address and data buses has been added to the chip. The speed of the chip has been increased substantially. The bus interface has been simplified. The chip parameter descriptions have been rewritten and elaborated on. The SCI- pin has been eliminated in favor of a pixel clock output pin. The DS- pin has been eliminated in favor of a dedicated test mode pin. The definitions and timing of the WEN and CMA buses have been changed. All of the figures and diagrams have been updated. Several configuration paramenter have been added. The appendicies have been updated. 1 February 1986 1 Toby Farrand Apple Confidential TFB Specification TABLE OF CONTENTS 1.0 INTRODUCTION 3 1.1 1.2 1.3 3 4 How to Read this Document System Configuration Features 2.0 DATA ORGANIZATION 5 3.0 CONTROL REGISTER DESCRIPTION 5 3.1 3.2 3.3 6 9 3.4 4.0 5.0 System Configuration Parameters Horizontal Timing Parameters Vertical Timing Parameters Initialization Procedure 11 12 SIGNAL DESCRIPTION 12 4.1 4.2 Inputs Outputs 13 15 Bus Operation 17 5.1 5.2 5.3 17 17 18 RAMCycle Data Transfer Cycle Refresh Cycle 6.0 Future Directions 18 6.0 Conclusion 19 Appendix A - Application Note. 20 Appendix B - Electrical Specifications. 24 Appendix C - Pinout and Mechanical Data. 31 1 February 1986 2 Toby Farrand Apple Confidential TFB Specification 1.0 INTRODUCTION One distinguishing characteristic of Apple's computer products is the tight coupling our machines have between their memory and video systems. This tight coupling results in products which have superior graphics in terms of resolution, speed and cost. This architecture's costs are significant,however, as the video refresh circuitry typically consumes between 40-50% of the available bus bandwidth. The demand for increased processor speed, …