RasterOps RGS14188 Users Guide Rev XA1

RasterOps RGS14188 User's Guide Preliminary REVISION XA 1 11/2/90 JEFF TINGLEY CONFIDENTIAL THIS DOCUMENT IS THE PROPERTY OF RasterOps REPRODUCllON OF THIS · DOCUMENT IS PROHIBITED . November 2, 1990 RGS14188 User's Guide 1.0 Introduction The RGS14188 Frame Buffer Controller (FBC) is a high-performance CMOS device that controls the video display and dynamic memory of a bit-mapped graphics system. Although the RGS14188 was designed to provide control of varying size, multi-port DRAMs (VRAMs) it works equally well with standard DRAMS and is easily interfaced to a variety of CPUs and buses. The principal role of an FBC is to provide an external processor with virtually unlimited access to (video) memory. It eliminates the delays and overhead caused by display update address generation, reloading shift registers, and DRAM refresh. Furthermore, the FBC reduces the amount of hardware needed to interface a RAM array and provides the user with the utmost flexibility. Highly programmable, the RGS14188 supports a broad range of raster-scan display systems with various resolutions and scan rates. Some of the major functions for RGS14188 FBC are: Generates all control signals necessary to control 256K, 1, 2, and 4 Megabyte VRAM devices, as well as those necessary to control conventional DRAMs of the same sizes. Generates the video synchronization and blanking signals necessary to control a CRT monitor. Accommodates processor data paths of arbitrary widths, working equally well with 8-bit to n-bit processors or bus architectures. Supports both interlaced and non-interlaced displays of essentially any display resolution. Automatically generates the special display-update cycles required by VRAM memories to maintain the CRT display. Automatically performs periodic RAM refresh cycles necessary to maintain the data stored. The block Diagram of a typical system using the RGS14188 is shown in Figure 1-1. 2 RGS14188 User's Guide November 2, 1990 CRT Control Signals RasterOps BGS14188 Host Bus Address Bus DRAM VRAM ROM Video Back End DAC Red Green Blue Data Bus Pixel Clock Figure 1-1 Typical System Using the RGS14188 2.0 Pinout and Signal Descriptions A functional drawing of the RGS14188 is given in Figure 2-1 and the pin number assignments are given in Figure 2-2. A description of each signal is given in the following section. The RGS14188 comes in a 120-terminal plastic quad flat package (PQFP). 3 November 2, 1990 RGS14188 User's Guide Address Input:; ( iP (pull down on (J.7..23] Multiplexed Row and Column Addr CASSelects -RAS1 -RAS2 -RAS3 CASStrobes -CASO -CAS1 -CAS2 -CAS3 Column-address Strobe Column-address Strobe Input latch Enable w ~a: -HCS Host Chip Select +HRD/-HWR ~ §::c -DT/-OE 1 Readylrransfer Acknowlege -PMHOLD (4111A) (4mA) Page Mode Hold Data Buffer Output Enable Vertical Blank ::'ASHIF.T 't~ :: :2}· Address Shift Horizontal Blan -BGACK (4mA) +BG Bus Grant Acknowlege Composite Syn< Bus Grant Input C…