0002 0154 Accelerator Board Model 800 Specification Rev D2

Accelerator board Model 800 Specification Revision 02 September 12, 1990 Dave Smith 1ssurn )\t J. !; 1 \j RasterOps Corporation oocuMENT PART# 0002-0154 ORIGINAL Introduction The Accelerator is a dedicated longword BITBLT-FILL engine optimized for the NuBus. The Accelerator has 8 modes of operation: FILL-CONSTANT, FILL-PA1TERN, PRAM-FILL, BITBLT, INVERT-FILL, INVERT-PA1TERN, INVERT-PRAM-FILL, and INVERT-BITBLT. In addition the programmer can enable BUS-LOCKING to prevent other NuBus masters from interrupting an operation.This function combined with automatic Block Transfer enable the Accelerator to fill data at a peak rate of 9 million pixels-per-second, and blit data at a peak rate of 4.5 million pixels-per second on a fast block mode video board. The Accelerator has been designed for maximum performance by minimizing the amount of software overhead required to initiate an operation and by a novel use of a large pixel Cache (SRAM). A flexible architecture has been created which allows any 32 bit address within the Macintosh computer to be accessed for each operation. A programmable translation memory (TRAM) is placed discontinuous data the motherboard to the video board. This function is required for the Macintosh Ilci and future machines with non-contiguous main memory. A large pixmap memory (PRAM) is included to allow offscreen pixmaps to reside locally and to be moved at high speed to the video cards. The Accelerator can support up to two Block-Mode capable videocards and an unlimited number of non-Block-Mode video cards. The Accelerator is not limited to just video cards, but can be used with memory cards as well. The Accelerator resides in its own NuBus slot and has a power consumption of 2 Amp. Reference Documents The following is a list of related documents for the Accelerator product: Schematic ,. 0002-0149 Assembly Drawing 0002-0150 PC Fab drawing/Artwork 0002-0151 Board List of Materials 0002-0152 Top Assembly LM 800 Manual 0700-0044 Block Diagram -AD(31 :0) TRANSLATION RAM I---' ADDRESSGENEPATOR CHIP N u .____ ADDRESS c 20-26 I---' 1-- B u s 1 I N T PIXMAP MEMORY 1---J 4-16 MEGS T 1-- E R F A c E ,. DATAGENERATCFl CHIP BK BYTE PIXEL CACHE ADD i--- DATA Accelerator Register Address Map FSFF Fxxx ID REGISTER FSFF C020 PRAM POINTER FSFFC01C MODE REGISTER FSFF C018 BLOCK COMPARE #2 FSFF C014 BLOCK COMPARE #1 FSFF C010 COUNT LENGTH FSFFCOOC SRAM POINTER FSFF COOS SEMAPHORE POINTER FSFF C004 DESTINATION POINTER FSFF COOO SOURCE POINTER FSFFA3FC TRANSLATION TRAM 1K BYTES FSFFAOOO FSFF9FFC PIXEL CACHE SRAM BK BYTES FSFF 8000 Pixel Cache SRAM The Pixel Cache SRAM (SRAM will be used from now on) is comprised of four 2048 x 8-25ns static rams arranged as long words. The SRAM may be written to or read from whenever the Accelerator is not busy with an operation (FILL, etc.). Locations 0- 1983 are used for BITBLT and Fll.L-CONSTANT mode, while locations 1984 - 2047 ar…