Apple Introduction To PowerPC Instruction Set Feb1993

R&D University • Introduction to PowerPC Instruction Set sity Introduction to PowerPC- Instruction Set: Rev 2, 2/93 ~~ 5 'f-Y"Ct_ c'+C) ,~.:z:::~.-o '"\-<."> P (; «.J'-€Jl Pc ~ 1!:::1I-..~1I'S PowerPC ( PowerPC Architecture Overview ~..J Book I - User Instruction Set Branch Unit Fixed Point Unit Floating Point Unit Book 11- Virtual Environment Book III - Operating Environment The First PowerPC Chips (Book IV) 1P'o~ 1!:::11-.. ~II'S PowerPC PowerPC Architecture Overview Book I - User Instruction Set Branch Unit Fixed Point Unit Floating Point Unit Book II - Virtual Environment Book 111- Operating Environment The First PowerPC Chips (Book IV) ~ 1!:::11-..~ RISC History and Lineages IBM 801 Branch Processor -> RT -> POWER -> PowerPC Berkeley RISC Register Windows -> 29K, SPARC Stanford MIPS -> MIPS, 88K, Alpha, ARM ~~.~u. • We'll look at several of these characteristics with real RiSe examples. Rise Fundamentals PipeLined Programming Model Compiler hae Substantial Effect on Performance Simple, Fixed Instruction Formats 10Cycie Decode, Large Number of Registers Simple Semantics 10Cycie Execution Stage Provide ·Prlmitlves- to Complier Only Loads & Stores Reference Memory LoadlStore Architecture Minimize Use of Critical Resources •. g., Condition Cod.s Caches Ron H......... 2iMI3 ~~.~ Instruction Execution Model ( ~-- F 1. Fetch Next Instruction 0 2. Decode Instruction, ~calculate Addresses, etch Operands, etc.) X 3. Perform Operation W 4. Write Back Results 5. Goto Step 1. Ron H.....-uno 21M3 ~1ClIme·~NI Ideal Instruction Sequence Instructions Require only 1 Clock per Stage 1. Fetch Next Instruction F 2. Decode Instruction, Calculate Addresses, Fetch Operands 0 3. Perform Operation X 4. Writ.Back Results W 11 12 11 11 5. Goto Step 1. Clocks ( "an H.......... IItIt3 • Cycle Time of ,each Stage is the same. PlpeLinlng Increase Throughput by Keeping Resources Busy ( Implement Each Instruction Stage by a Separate Unit - Pipe Stage. Each Pipe Stage Operates on a DIHerent Instruction In a Cycle Don't Wait for An Instruction to Complete before Starting the Next Does Not Reduce Latencyl! ~WMI'IPC~-~11liI PlpeLined Instruction Sequence Instructions Require only 1 Clock per Stage ( 1. Fetch Next Instruction F 2. Decode Instruction, Calculate Addresses, Fetch Operands 0 3. Perform Operation X 4. WriteBack Results W 11 12 13 14 15 11 12 13 14 11 12 13 11 12 5. Goto Step 1. CI_ ~ Ron H...,..... 2ItIU ~~-~ Instruction Formats ( tid b ¥ !-form OP 8-form OP Bol BI D-form OP RxlRA X-form OP RT IRA RB I XOP XO-form OP RTIRA RB fl XOP A-form OP RS IRA RB I RC IXOp~ filaddfl,f2,B,fl M-form OP RS IRA RBI MB I ME ~ Ron H......... 2ItII1 Dise24 Dise14 ~D 1Nl\)tZ addl 1'5,1'4,123 I. 1'5,211(1'4) Imm16 n and r),r4,~ and. rS,r4,~ I .. r),r4,~ fl add rS,r4,~ addeo. r'.r4.rS rl_ rS,r4,~,2II,31 ~ ~1C1JSJM-~ Branches - The Problem Branches Leave "Bu…