Apple PowerPC Runtime Architecture Oct1992

R&D University PowerPC Runtime Arch itectu re PowerPC Runtime Architecture, October 14, 192 R&D University PowerPC Runtime Architecture •• • II • Itt t I Alan Lillich Developer Tools Group ( PowerPC Runtime Archttecture Version 1.1 .. _._-_. -" ... __._----- _.--_.___.-_.-___ - - - - _ .--_._. .. .. .. ... .. 1 Day 1 Content . . . .:' . . . . . . ': ....... :: .... ::. :.' · .. .. · .. . .. · ~.:. .... :.~ ::,:., ~':..~.\: . ... . : ~ 'C' :;::. ''- • ',' P_PC Runtime Archlectu.. Version 1.1 • '- • '- • '-'- R&D University Alan Lilich " Apple Confidential 11·10--112 2 2 Schedule for Today c . .. ....... . . First Day of Course a I lUlU urluan II I II UDDUDI I II r • Background Information • Program Components • Global Addressing • Stack Frames • Calling Conventions p""""pc Runtime Architecture Version 1.1 c R&D University Alan Lillich - Apple Confidential 11·1D--92 3 3 Background Information .' • Hardware Architecture - Review features that influence software architecture • Miscellaneous - Software architecture derived from AIX - Assembly programmers must do what compilers do! - We're only talking about 32-bit software • Special code can take advantage of 620 • No fully 64-bit O/S planned yet P ......rPC Runtime Architecture R&D Unive..iy Version 1.1 Alan LiNich " Apple Confidential 11-10-·92 4 4 ,. Background Information c' . .. .. Definitions • Effective Address: 3~b;-t-5 - The "register size" addresses used by PowerPC software. • Virtual Address: L '.1- '80 ~ - A "large" address used by PowerPC hardware during address translation. • Volatile Register: - A register whose contents need not be the same on return from a call as before. PowerPC Runtime Archftec:ture V.aion 1.1 R&D UnivelSiIy Alan UHich It Apple Confidential 11·10--92 5 5 CPU Architecture Key Instruction Set Features alia IIU II UIIUIIUI I I 11111111111111 "nann I I a I 1111111 1m III I II I I I • Three basic units => cheap branches • Typical load/store architecture • Generally three register operands • Fixed length instructions - Few memory addressing modes • 32 bit only PowerPC Runlime Architecture Version 1_1 R&D University Alan URich " Apple Confidential 11-10--92 6 6 CPU Architecture . Key Instruction Set Features , , II I I I II 1111 I • Lots of registers - 32 General Purpose (32/64 bit) - 32 Floating Point (64 bit) - 8 Condition Code "Fields" (4 bits: LT, GT, EQ, SO) • A large set of (mostly) reduced instructions • Effective Address versus Virtual Address PowerPC Runtime AR:hilectU18 Version 1.1 R&D University Alan LiRich II Apple Confidential 7 11-10--92 7 CPU Architecture .' . ~v-L*,o........ 5 • Unconditional Branches ~D'J... ~~ ~s - PC relative, 24-bit ~diate displacement (+32MBr • Conditional Branches - PC relative, 14-bit immediate displacement (+32KB) - Indirect through Link or Count Register • Displacements - Are signed and in words (inst…