Unisoft Lisa Kernel Aug1983

Fri Sep ivec.s 5 19:08:57 1986 1 Copyright 1982 UniSoft Corporation bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr Interrupt vector dispatch table One entry per interrupt vector location .text .globl dispatc: bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr bsr _dispatc, __pmvect, _tevect lfault lfault lbuserr laddrerr lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault llintr kbintr pis pi4 pi3 scintr !Uni lsyscall lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault 2 3 5 6 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Reset: Initial SSP Reset: Initial PC Bus Error Address Error Illegal Instruction Zero Divide CHK Instruction TRAPV Instruction Privilege Violation Trace Line 1010 Emulator Line 1111 Emulator (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) Spurious Interrupt Level 1 pp 0, sony, vert retrace (clock) Level cops, mouse, rtclock, buttons Level exp slot 3 (default 2-port card) Level exp slot 2 (default 2-port card) Level exp slot 1 (default 2-port card) Level sec chip Level Interrupt Autovector system Call TRAP Instruction Vector TRAP Instruction Vector TRAP Instruction Vector TRAP Instruction Vector TRAP Instruction Vector TRAP Instruction Vector TRAP Instruction Vector TRAP Instruction Vector TRAP Instruction Vector TRAP Instruction Vector TRAP Instruction Vector TRAP Instruction Vector TRAP Instruction Vector TRAP Instruction Vector TRAP Instruction Vector (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) (User Interrupt Vector) (User Interrupt Vector) (User Interrupt Vector) lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault lfault 67 68 69 70 71 72 73 74 75 76…