ApplROM.A.Lst
ApplROM.A.Lst
NuBus · 1984 · LST
| Filename | ApplROM.a.lst |
|---|---|
| Size | 0.07 MB |
| Year | 1984 |
| Subsection | apple / Zorro_Coax-Twinax_Card / diag |
| Downloads | 4 |
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Contents
MC68020 Assembler - Ver 2.88 14-Dec-88 Page 1
Copyright Apple Computer, Inc. 1984-1987
Loc F Object Code Addr M Source Statement
;-------------------------------------------------------------------
;
; (c) Apple Computer, Inc. 1987
; All rights reserved.
;
;-------------------------------------------------------------------
;
; File : CommROM.a
; Author : Michael Klassen, June 8, 1987.
; Description : This file contains the data structure definition
; for the MCP Comm Engine card.
;
;-------------------------------------------------------------------
; Modification History :
;
; 7 March 1988: WHJW: mods to support multiple ROM vers w/ same source code
; 8 July 1988: WHJW: Correctly identified slot resource list entries
;-------------------------------------------------------------------
;*************************************************************
;Constants
;*************************************************************
INCLUDE 'CommDeclr.h'
;*************************************************************************
;
; CommDeclr.h:
; Constants used for Smart card Diagnostics
0007 FFFE STACK EQU $7FFFE ; offset of stack in card RAM
0001 0000 ROMSize EQU (64*1024) ; ROM = 64K
0000 0000 OFF equ 0
FFFF FFFF ON equ -1
0000 0000 PASS equ 0
FFFF FFFF FAIL equ -1
0000 0001 WAIT equ 1
; Delay constants in microseconds
0000 0D00 TimeDBRA equ $D00 ; (word) location: # of DBRA instructions/mSecond
0000 01F4 WaitCount equ 500 ; timeout - wait for power_on finish
0000 0004 TimeCnt equ 4 ; timeout for IOP test
0000 0010 TimerWait equ 16 ; timeout for Timer test
0000 0004 Delay equ 4 ; Reset delay
; variable offsets into card RAM
0000 0100 WaitFlag equ $100 ; power_on wait flag
0000 0102 TstStatus equ $102 ; test status bit flags
0000 0104 TimeFlag equ $104 ; flag for timer test
0000 0106 HostFlag equ $106 ; flag for host reset test
0000 0108 ResetFlag equ $108 ; flag to control reset code
0000 010C IOPFlag equ $10C ; flag for IOP interrupt test
0000 010E CRCCalcAddr equ $10E ; ROM calculated CRC value
0000 0112 WriteLoc equ $112 ; Location of Nubus write/read test
;rteAddr equ $116 ; rte for interrupt vectors (no longer used)
0000 0118 timeCountAddr equ $118 ; address of firmware timer counter
0000 011C RAMSizeAddr equ $11c ; Size of card RAM in bytes
0000 0120 TASStatusAddr equ $120 ; returns test & set card status to 020
0000 0122 NMRQFlag equ $122 ; flag for NMRQ test
0000 0128 BusErrAddr equ $128 ; flag for bus error
0000 012C InitA5Addr equ $12c ; Used for finding data block
0000 0130 CodeOffset equ $130 ; Used for finding code block
0000 0134 VendPowerStatus equ $134 ; return status from vendors power-up code
0000 0138 VendPrimaryStatus equ $138 ; return status from vendors Primary init code
0000 013C ExceptionPC equ $13C ; PC stored here after exception takes place
0000 0140 ErrorAddr equ $140 ; data addr stored here after bus or addressing error
0000 0144 RAMErrAddr equ $144 ; if RAM error occurs, its address stored here
0000 0148 L1IntAddr equ $148 ; Mac processor stores new Timer interrupt loc here;
; then calls SetL1Interrupt to set it safely.
; card space to $180 to $200 reserved for temporary data values only
00E0 0000 testROMAddr equ $e00000 ; location of Fremont board tester ROM
0080 0008 ROMversion equ $800008 ; location of Mac II ROM version number
; Test status bit masks
MC68020 Assembler - Ver 2.88 14-Dec-88 Page 2
Copyright Apple Computer, Inc. 1984-1987
Loc F Object Code Addr M Source Statement
0000 FFFF testsDefined equ $ffff ; currently defined test bits
0000 FFFE DLTestMask equ $fffe ; sliding 5 data line test
0000 FFFD RAMTestMask equ $fffd
0000 FFFB testPatternMask equ $fffb ; signals PROM burned incorrectly
0000 FFF7 CRCTestMask equ $fff7 ; Clears CRC test bit
0000 FFEF VendPowerupMask equ $ffef
0000 001F PowerMask equ $1F
FFFF FFDF BusMask equ $FFFFFFDF ; clears Nubus write/read test bit
FFFF FFBF HostMask equ $FFFFFFBF ; clears host reset test bit
FFFF FF7F TimeMask equ $FFFFFF7F ; clears timer test bit
FFFF FEFF IOPMask equ $FFFFFEFF ; clears IOP test bit
FFFF FDFF VendMask equ $FFFFFDFF ; clears vendor test bit
FFFF FBFF NMRQMask equ $FFFFFBFF ; clears NMRQ test bit
; Card control switch offsets
00C0 0000 ExtReg equ $C00000 ; Nubus extension register (write) or unreset (read)
00C0 0002 TimerSet equ $C00002 ; Timer interrupt switch (read)
00C0 0008 ClrIOPIntr equ $C00008 ; Clear Interrupt IOP request (read)
00C0 000A SetIOPIntr equ $C0000A ; Set Interrupt IOP request (read)
00C0 0004 ClrHostIntr equ $C00004 ; Clear Host Interrupt request (read)
00C0 0006 SetHostIntr equ $C00006 ; Set Host Interrupt request (read)
00F0 0000 Reset equ $F00000 ; programmed reset of 68000 (write)
00B0 0000 SetTASAddr equ $B00000 ; Prime card for an offcard TAS instruction
; Pointers to interrupt test routines
00FF FF60 SetL1Addr equ $FFFF60
00FF FF80 TimeAddr equ $FFFF80
00FF FFA0 HostAddr equ $FFFFA0
00FF FFC0 IOPAddr equ $FFFFC0
; test patterns
5555 5555 testWord1 equ $55555555 ; power-up RAM test data word
AAAA AAAA testWord2 equ $aaaaaaaa
5A5A 5A5A testWord3 equ $5a5a5a5a
55AA 55AA testWord4 equ $55aa55aa
5A93 2BC7 bTestPattern equ $5a932bc7 ; test pattern in identifier block
AAAA 5555 testROMSig equ $aaaa5555 ; PVT test ROM Signature
; format header block offsets
00FF FFFF fBlockLoc equ $ffffff ; 0, 1, 2, 3 bytelanes begins here
0000 0000 byteLanes equ 0
FFFF FFFB testPatLoc equ -5
FFFF FFFA formatLoc equ -6
FFFF FFF5 CRCLoc equ -$b
FFFF FFF1 lengthLoc equ -$f
FFFF FFEB CommIDLoc equ -$15 ;used to identify GMSIOP card application
FFFF FFE9 VendIDLoc equ -$17 ;used to identify specific hardware configuration
0000 C3D2 CommID equ $c3d2 ;GMSIOP card ROM identifier
0000 0001 MacID equ 01 ; Mac II ROM ID
;Equates shared by asmlib.a & exceptions.a
0000 00F7 mode24mask equ $F7
0000 0008 mode32mask equ $8
50F0 2000 addrPort equ $50F02000 ;32 bit hardware switch; no longer accessed directly
0000 0CB2 MMU32bit equ $0CB2 ;(byte) boolean reflecting current 020 machine MMU mode
00FF FFEC codePtr equ $FFFFEC
0000 0A7C MyIntHndl equ $a7c ;handle in 020 Application scratch memory
0000 0A80 AppScratch equ $a80 ;last 4 bytes of appl scratch area
A9FF _Debugger OPWORD $A9FF
A11E _NewPtr OPWORD $A100+30
A01F _DisposPtr OPWORD $A000+31
A05D _SwapMMUMode OPWORD $A05D ;from traps.a
A075 _SIntInstall OPWORD $A075
A076 _SIntRemove OPWORD $A076
A9F2 _Launch OPWORD $A9F2
MACRO
_m32
move.l d0, -(a7)
move.l #1, d0
_SwapMMUMode
move.l (a7)+, d0
MC68020 Assembler - Ver 2.88 14-Dec-88 Page 3
Copyright Apple Computer, Inc. 1984-1987
Loc F Object Code Addr M Source Statement
ENDM
MACRO
_m24
move.l d0, -(a7)
move.l #0, d0
_SwapMMUMode
move.l (a7)+, d0
ENDM
INCLUDE 'Application.h'
;==================================================================================
; File: Application.h
;
; Function: Application card ROM constants stored here
;
0042 0001 bcpRIC equ $420001 ; 8344 remote interface configuration register
0040 0001 bcpPC equ $400001 ; Dummy address for writing to 8344 PC
0040 0001 bcpDRAM equ $400001 ; 8344 Data RAM address base
0040 7C15 bcpGoodData equ $3E0A * 2 + bcpDRAM ; Test data
0040 7C17 bcpBadData equ $3E0B * 2 + bcpDRAM ; Bad data read back
0040 7C19 bcpErrAddrHi equ $3E0C * 2 + bcpDRAM ; Failed memory address, high order
0040 7C1B bcpErrAddrLo equ $3E0D * 2 + bcpDRAM ; Failed memory address, low order
0040 7C1D bcpTestErr equ $3E0E * 2 + bcpDRAM ; BCP test error bits
0040 7C1F bcpTestState equ $3E0F * 2 + bcpDRAM ; BCP test states
0040 7C01 bcpComm equ $3E00 * 2 + bcpDRAM ; BCP - 68k communication area
0040 8001 bcpDMEnd equ $4000 * 2 + bcpDRAM ; Last data memory + 1
;
; - RIC selections
;
0000 0034 RIC_START equ $34 ; Start 8344 execution
0000 0030 RIC_DRAM equ $30 ; Select 8344 Data RAM
0000 0034 RIC_DRAM_RUN equ $34 ; Select 8344 Data RAM and do not stop 8344
0000 0031 RIC_IMEM equ $31 ; Select 8344 Instruction memory
0000 0032 RIC_PC_LO equ $32 ; Select 8344 Program Counter low byte
0000 0033 RIC_PC_HI equ $33 ; Select 8344 Program Counter high byte
;
; - BCP test states
;
0000 0000 bcpIDLE equ $00 ; BCP test not started
0000 0001 bcpRUNNING equ $01 ; BCP test in progress
0000 0002 bcpDONE equ $02 ; BCP test completed
;
; - BCP Tests entry points, low bytes
;
0000 0020 BT_POR equ $20 ; 8344 POR Test starts at 0020
;
; - BCP test error bits
;
0000 0001 bcpRegErr equ $01 ; BCP register test failed
0000 0002 bcpLoopErr equ $02 ; BCP loop back test failed
0000 0010 bcpRamErr equ $10 ; BCP data RAM test failed
0000 0013 bcpError equ bcpRegErr + bcpLoopErr + bcpRamErr
;
; Misc.
;
0000 0800 BCP_IM_SIZE equ $800 ; size of bcp instruction memory (I.M.)
0000 1000 bcp_rdback equ $0001000 ; start location to store readback from 8344 I.M.
0002 0000 WaitBCPDone equ $00020000 ; loop count waiting for 8344 to finish testing
0000 5A6F VendID equ $5a6f ;unofficial Zorro Vendor ID
MC68020 Assembler - Ver 2.88 14-Dec-88 Page 4
Copyright Apple Computer, Inc. 1984-1987
Loc F Object Code Addr M Source Statement
;----------- sResource Directory stuff ;<Id OF>
0000 0001 sRsrc_Board EQU 1 ;Board sResource
0000 000A CommBoardId EQU $A ;Officially defined by Developer Technical Support
0000 0004 ROMRevLevel equ 4 ;ROM revision level (now D) must be < 9
0000 0080 sRsrc_CPU EQU 128 ;identify CPU & memory resources
0000 0081 sRsrc_Comm1 EQU 129 ;comm type 1
0000 0082 sRsrc_Comm2 EQU 130 ;comm type 2
0000 0083 sRsrc_Comm3 EQU 131 ;comm type 3
0000 0084 sRsrc_Comm4 EQU 132 ;comm type 4
0000 008C sRsrc_sMemory EQU 140 ;2nd leved sResource (not seen directly by slot manager)
0000 0096 CatsMemory EQU 150 ;not defined by DTS, 2nd level sRrsource
0000 0080 MinorRAMAddr EQU 128
0000 0082 MinorROMAddr EQU 130
0000 0084 MinorDeviceAddr EQU 132
0000 000A CatCPU EQU $000A ;
0000 0001 Typ68000 EQU $0001 ;
0000 FFFF DrSwNotThere EQU $FFFF ;Apple MCP has 68K, no on-board driver
0000 0001 DrHwAMCP EQU $0001 ;First generation Apple MCP cards
0000 0006 CatCommunication EQU $0006 ;mb CatInterface?
0000 0013 Typ3270 EQU $0013 ;vanilla 3270 for Zorro card 8/23/88
;DrSwNotThere EQU $FFFF ;Apple MCP has 68K, no on-board driver
;DrHwAMCP EQU $0001 ;First generation Apple MCP cards
;CatCommunication EQU $0006 ;mb CatInterface?
;Typ3270 EQU $0013 ;vanilla 3270 for Zorro card 8/23/88
;DrSwNotThere EQU $FFFF ;Apple MCP has 68K, no on-board driver
0000 0006 DrHwA3270_5250 EQU $0006 ;Apple 3270/5250 NB card (Zorro)-implies 8344 chip
;CatCommunication EQU $0006 ;mb CatInterface?
0000 000A Typ5250 EQU $000A ;5250 protocol (actual DTS constant is Typ32705250)
;DrSwNotThere EQU $FFFF ;Apple MCP has 68K, no on-board driver
;DrHwAMCP EQU $0001 ;First generation Apple MCP cards
;CatCommunication EQU $0006 ;mb CatInterface?
;Typ5250 EQU $000A ;5250 protocol (actual DTS constant is Typ32705250)
;DrSwNotThere EQU $FFFF ;Apple MCP has 68K, no on-board driver
;DrHwA3270_5250 EQU $0006 ;Apple 3270/5250 NB card (Zorro)-implies 8344 chip
;Include files
PRINT ON
00000 CommROM MAIN
00000 STRING C
00000
00000
00000 ;===============================================================================
00000 ; Power-On test
00000 ; The following jsr PowerOn must be the first instruction of code in the ROM.
00000 ; PowerOn tests RAM, ROM, & will then call the Vendor Powerup test defined in ApplPoweron.a
00000 ;===============================================================================
00000
00000 IMPORT PowerOn ;from powerup.a
00000
00000 4EBA 0000 jsr PowerOn
00004
00004 ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
00004 ; Resource Directory
00004 ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
00004 ; <ID> <OFFSET/DATA>
00004 _sRsrcDir OSLstEntry sRsrc_Board,_sRsrc_Board ;<sRsrc_Board> <Board sRsrc List offset>
00004 0100 001C 1 DC.L (sRsrc_Board<<24)+((_sRsrc_Board-*)**$00FFFFFF) ;<C444/19nov86>
MC68020 Assembler - Ver 2.88 14-Dec-88 Page 5
Copyright Apple Computer, Inc. 1984-1987
Loc F Object Code Addr M Source Statement
00008 OSLstEntry sRsrc_CPU, _sRsrc_CPU ; defines CPU, MCP architecture
00008 8000 00A8 1 DC.L (sRsrc_CPU<<24)+((_sRsrc_CPU-*)**$00FFFFFF) ;<C444/19nov86>
0000C OSLstEntry sRsrc_Comm1, _sRsrc_Comm1 ;category Communications
0000C 8100 0148 1 DC.L (sRsrc_Comm1<<24)+((_sRsrc_Comm1-*)**$00FFFFFF) ;<C444/19nov86>
00010 OSLstEntry sRsrc_Comm2, _sRsrc_Comm2 ;category Communications
00010 8200 0180 1 DC.L (sRsrc_Comm2<<24)+((_sRsrc_Comm2-*)**$00FFFFFF) ;<C444/19nov86>
00014 OSLstEntry sRsrc_Comm3, _sRsrc_Comm3 ;category Communications
00014 8300 01B4 1 DC.L (sRsrc_Comm3<<24)+((_sRsrc_Comm3-*)**$00FFFFFF) ;<C444/19nov86>
00018 OSLstEntry sRsrc_Comm4, _sRsrc_Comm4 ;categ…
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