Mc 68060
Contents
Date: Fri, 23 Jul 1993 02:32:16 -0800
From: lkchun@heartland.bradley.edu (Lance K. Chun)
Subject: MOTOROLA 68060 FACTS !
***** START OF CROSSPOSTED MESSAGE
From: TOERNE@RHEIN IAM UNI-BONN Date: 05-24-93 04:33
To: ALL Msg#: 13975
Subj.: MOTOROLA 68060 FACTS !
Area: U-LIAMIGA
Here it finally is:
MOTOROLA SEMICONDUCTOR PRODUCT INFORMATION on the MC68060
(a really thing worth reading because this time it's not one's opinion
but pure objective information from a reliable source - ;-))
------------------------------------------------------------------------ 1
Product Brief
Forth-Generation 32-Bit Microprocessor
The MC 68060 is a superscalar, high-performance, 32-bit microprocessor
providing a low-power mode of operation. The MC68060 is fully compatible
with all previous members of the M68000 family. The MC68060 features dual
on-chip caches, fully independent demand-paged memory management units
(MMUs) for both instructions and data, dual integer execution pipelines,
on-chip floating-point unit (FPU), and branch target cache. A high degree
of instruction execution parallelism is achieved through the use of a full
internal Havard architecture, multiple internal buses, independent execu-
tion units, and dual instruction issue within the instruction execution
controller. Power management is also a key part of the MC68060 architec-
ture. The MC68060 offers a low-power mode of operation that is accessed
through the LPSTOP instruction, allowing for full power-down capability.
The MC68060 design is fully static so that when circuits are not in use,
they do not draw power. Each unit can be disabled so that the power is
used only when the unit is enabled and executing an instruction. Figure 1
illustrates a block diagram of the MC68060.
+------------------------------------------+
+-+
|Integer unit | |
|
| +----------------------------+ | |
|
| |Instruction fetch controller| | |
|
| | +------+ +--------+ | | +----------------------------+ |
|
| | |Branch|<-| IA |----------->| +----------+ +----------+ | |
|
| | |Cache | |Generate| | | | |Intruction|->|Intruction| | |
|
| | | | +--------+ | | | | ATC | | Cache | | |
|
| | | |->|Intruct.|<-----------| +----------+ +----------+ | |
| Intruct.
| | | | | Fetch | | | | ^ ^ |<-|
| Address
| | +------+ +--------+ | | | | | | |
|<------->
| | | Early | | | | +------------------+ | |
|
| | | Decode | | | | | Instruction | | |
|
| | +--------+ | | | | Cache | | |
|…
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