Well, theres multiple ways I can go about it.
As far as clock speed is controlled, I will likely use an ICS511 which I have in the past, its a jumper-adjustable PLL clock multiplier. So I can 1.5X or 2X, or etc the base system clock which is 16Mhz
but also include a jumper to run at 16mhz, or use an external crystal. But I know for a fact I have to use and/nor/flipflop gates to sync up with the 16mhz clock due to the VPA/VMA/E synchro bus to talks to the SCC/VIA.
I do need to figure out how DTACK is handled. I think its generated by the RAM controller instead of the GLU on the Backlit model. This is important because if I double the clock speed, that means there is going to be two wait states inserted for every single wait state on the bus, (Macintosh LC anyone?) and if DTACK comes too early then it may cause me issues with RAM accesses. Then again, since the macintosh will be treated as a 16-bit port to a 32-bit processor, its going to take two cycles for every 32-bit data transfer anyway. (again, Macintosh LC anyone?)
What would be awesome is if I can attach the 8MB of SRAM directly on the 030 CPU and make it 32-bit RAM instead of the 16-Bit RAM onboard. that would increase performance drastically, BUT the thing that gets in the way of this is the Overlay function. Somehow I would have to ignore the system board during RAM read/write accesses. But at the same time still follow the overlay during RESET
hmmmm soo many things. lol.
As far as clock speed is controlled, I will likely use an ICS511 which I have in the past, its a jumper-adjustable PLL clock multiplier. So I can 1.5X or 2X, or etc the base system clock which is 16Mhz
but also include a jumper to run at 16mhz, or use an external crystal. But I know for a fact I have to use and/nor/flipflop gates to sync up with the 16mhz clock due to the VPA/VMA/E synchro bus to talks to the SCC/VIA.
I do need to figure out how DTACK is handled. I think its generated by the RAM controller instead of the GLU on the Backlit model. This is important because if I double the clock speed, that means there is going to be two wait states inserted for every single wait state on the bus, (Macintosh LC anyone?) and if DTACK comes too early then it may cause me issues with RAM accesses. Then again, since the macintosh will be treated as a 16-bit port to a 32-bit processor, its going to take two cycles for every 32-bit data transfer anyway. (again, Macintosh LC anyone?)
What would be awesome is if I can attach the 8MB of SRAM directly on the 030 CPU and make it 32-bit RAM instead of the 16-Bit RAM onboard. that would increase performance drastically, BUT the thing that gets in the way of this is the Overlay function. Somehow I would have to ignore the system board during RAM read/write accesses. But at the same time still follow the overlay during RESET
hmmmm soo many things. lol.