Basically the CPLD is going to be performing 3 functions, Well 4.
1. Setup A0,A1,SIZ0,SIZ1 to tell the CPU that its working with 16-bit bus cycles.
2. Handle VPA/VMA/E Sync for synchronous bus accesses.
3. Handle decoding for the FPU, Decoding FC0/FC1/FC2 for CPU space, and decoding a couple address lines to determine that its the primary co processor, as the 68K can address multiple coprocessors.
4. Handle bus-mastering, gaining control and turning off the primary processor.
5. Adding propogation delay via flipflops/AND gates to fix the bus-cycle pipelining. the 68020+ is a 3 clock period bus cycle whereas the 68000 is 4. So a 1 clock cycle delay needs added to step1 for the DSACK/AS/DS.
For getting control of the bus, its like this:
First you toggle and hold the Bus Request line. The CPU then returns back a Bus Grant. The device that requested bus access, Then recieves the bus Grant. Once the Address/data strobes have returned to an idle state with the main CPU clearing the current bus cycle, the Bus Grant Acknowledge line is then toggled and held by the device requesting the master. it continues to hold it, along with Bus Request until its ready to give up control.
When your finished, you release bus request, and bus grant acknowledged. The main CPU then looks at the bus state before releasing Bus Grant. And once its fine, the processor latches back in and takes over.
So CPLD toggles bus request, waits for Bus grant. CPLD gets bus grant from CPU. CPLD then checks bus states with a decoder (make sure current cycle is complete), then CPLD latches and hold Bus Grant Acknowledge until its done with the bus. This is to prevent bus contention, to prevent the bus mastering device from taking over before the CPU is finished with the current cycle.
Electronically, bus grant would be ANDed with the DSACK/UDS/LDS/AS, output of the AND would then be going into a flipflop which would latch onto the BGACK, and hold it until the flipflop is cleared. Its cleared when bus request or bus grant goes into inactive state.
Inactive state happens when the accelerator gives up control to another bus master device (which the SE/portable doesnt have so not important), or the system is power cycled or reset. Multiple bus masters would need another chip on board to handle arbitration prioritization. such as a DMA controller. So if for example the SCSI controller is DMA capable, and is a bus master (add in card) and wants the bus, the arbitrator would get the request from that slot. This would cause BGACK to get released and then the SCSI takes over the bus until its finished. Then the CPU card tries to take back over when it goes inactive again. This can get complicated.
But again for the portable, or any other low power 68K mac, there is no other bus mastering that I am aware of. The video generation circuit remains in question though, especially for SE as its constantly pulling from the RAM for its framebuffer, without the CPU.
If you want to get really clever, you could attach the bus mastering logic to another address-decoded register. So the CPU accelerator is not doing anything, or running until you write the register via a poke.
So, like sonnet, you load an extension which sees and turns on the card, card then takes over the bus and assumes control. So in a situation where you need to save battery life, or a program is unstable with the accelerator, you can turn it off via a control panel.
As far as CPLDs are concerned, I want to stick with xilinx as thats who I have a programming cable for. Knock on wood, I havent blown up 1 CPLD in my RAM card project, But I did use 74 series level shifter style buffers, And, I used resistors between any CPLD lines that didnt route through the buffer.
1. Setup A0,A1,SIZ0,SIZ1 to tell the CPU that its working with 16-bit bus cycles.
2. Handle VPA/VMA/E Sync for synchronous bus accesses.
3. Handle decoding for the FPU, Decoding FC0/FC1/FC2 for CPU space, and decoding a couple address lines to determine that its the primary co processor, as the 68K can address multiple coprocessors.
4. Handle bus-mastering, gaining control and turning off the primary processor.
5. Adding propogation delay via flipflops/AND gates to fix the bus-cycle pipelining. the 68020+ is a 3 clock period bus cycle whereas the 68000 is 4. So a 1 clock cycle delay needs added to step1 for the DSACK/AS/DS.
For getting control of the bus, its like this:
First you toggle and hold the Bus Request line. The CPU then returns back a Bus Grant. The device that requested bus access, Then recieves the bus Grant. Once the Address/data strobes have returned to an idle state with the main CPU clearing the current bus cycle, the Bus Grant Acknowledge line is then toggled and held by the device requesting the master. it continues to hold it, along with Bus Request until its ready to give up control.
When your finished, you release bus request, and bus grant acknowledged. The main CPU then looks at the bus state before releasing Bus Grant. And once its fine, the processor latches back in and takes over.
So CPLD toggles bus request, waits for Bus grant. CPLD gets bus grant from CPU. CPLD then checks bus states with a decoder (make sure current cycle is complete), then CPLD latches and hold Bus Grant Acknowledge until its done with the bus. This is to prevent bus contention, to prevent the bus mastering device from taking over before the CPU is finished with the current cycle.
Electronically, bus grant would be ANDed with the DSACK/UDS/LDS/AS, output of the AND would then be going into a flipflop which would latch onto the BGACK, and hold it until the flipflop is cleared. Its cleared when bus request or bus grant goes into inactive state.
Inactive state happens when the accelerator gives up control to another bus master device (which the SE/portable doesnt have so not important), or the system is power cycled or reset. Multiple bus masters would need another chip on board to handle arbitration prioritization. such as a DMA controller. So if for example the SCSI controller is DMA capable, and is a bus master (add in card) and wants the bus, the arbitrator would get the request from that slot. This would cause BGACK to get released and then the SCSI takes over the bus until its finished. Then the CPU card tries to take back over when it goes inactive again. This can get complicated.
But again for the portable, or any other low power 68K mac, there is no other bus mastering that I am aware of. The video generation circuit remains in question though, especially for SE as its constantly pulling from the RAM for its framebuffer, without the CPU.
If you want to get really clever, you could attach the bus mastering logic to another address-decoded register. So the CPU accelerator is not doing anything, or running until you write the register via a poke.
So, like sonnet, you load an extension which sees and turns on the card, card then takes over the bus and assumes control. So in a situation where you need to save battery life, or a program is unstable with the accelerator, you can turn it off via a control panel.
As far as CPLDs are concerned, I want to stick with xilinx as thats who I have a programming cable for. Knock on wood, I havent blown up 1 CPLD in my RAM card project, But I did use 74 series level shifter style buffers, And, I used resistors between any CPLD lines that didnt route through the buffer.