I got some documents that I will have to dig up, but I have schematics of an accelerator with FPU that is discrete logic, and I have a couple sheets on an accelerator that uses PALs with PALASM. 

And of course there is the motorola Application Note AN944 which explains how to use a 68020 in a 68000 system. it was located and posted in my RAM thread. 

There is also a working accelerator out there that uses a large scale FPGA with 68K softcore