The issue is that if the address decoding is complete, which one would guess it would be on a last-generation Quadra, then the RAM cycle generation wouldn't happen when addresses are accessed outside of the normal RAM area. So while one could simply put a 74HTC138 onto A31, A30, and A29 and assume that everything else mapped in the Quadra is in the 0-512 meg range and activate a bank of memory in the 512-1024 meg range, you'd also have to have the circuitry to strobe in the full address.Exactly, but the 68040 should have plenty of memory select lines available and it's very well documented. The Pro Level Quadras have at least four RAM slots, do they not? It wouldn't be as easy as hacking a IIfx by hijacking the existing parity lines with a few cuts and very short rework wires, but it might be possible. You'd need to be careful about keeping all the lines at similar lengths to avoid timing issues . . .. . . but it might be a lot of fun to look into! }
Now if someone were to make some huge straight memory chips (meaning all of the address lines are run out to pins and the data lines are separate), this would be much more doable. Wiring memory to, say, an 8 bit processor was something a 12 year old could do (I did!)