Ahhhh! I always get my micros and nanos goofed up! You are right, they are 55 NANO-second read access time, which is actually faster than the ones I lost. Hmmm...
I built the sockets with AT29C020 ROMs in mind and these are AT49F040 ROMs. Comparing datasheets, I see the only difference is A18 on pin 1 which is NC on the older ROMs. I originally added address bus wires for A17 and A18 just in case I ever got these 4Mbit chips, so I think that's okay.
So these ROMs I'm working with have the following pins:
A0:A18 (Address pins)
D0
7 (Data I/O pins)
VCC (+5V)
GND (0V)
/WE (Write Enable) = 1
/OE (Output Enable) = 0
/CE (Chip Enable) = 0
I will check logic levels on /WE and /OE. /CE should be okay because the Mac will need to control that to multiplex other devices, i.e. RAM, NuBus, etc. Whatever shares the same data pathways. I'll keep you posted.
I built the sockets with AT29C020 ROMs in mind and these are AT49F040 ROMs. Comparing datasheets, I see the only difference is A18 on pin 1 which is NC on the older ROMs. I originally added address bus wires for A17 and A18 just in case I ever got these 4Mbit chips, so I think that's okay.
So these ROMs I'm working with have the following pins:
A0:A18 (Address pins)
D0
7 (Data I/O pins)VCC (+5V)
GND (0V)
/WE (Write Enable) = 1
/OE (Output Enable) = 0
/CE (Chip Enable) = 0
I will check logic levels on /WE and /OE. /CE should be okay because the Mac will need to control that to multiplex other devices, i.e. RAM, NuBus, etc. Whatever shares the same data pathways. I'll keep you posted.