I noticed in the spec sheet that these are actually 90ns, not 50 or whatever I said. The bullet points up on top are a little misleading. That should not be an issue anyway though. I'm starting to think about incompatible logic levels. Maybe this is CMOS and it expects TTL or something. I was pretty sure that the old and the new are both CMOS though. I really believe that all pins are connected properly now too, and the ROMs verified after burn. I will be double-checking all 128 connections at some point. It is unlikely that there is a short because the ROM simm works fine. If address or data lines were shorted together, that would prevent the simm from working too.

So I guess I'll check continuity of address lines between the 4 sockets and the simm slot, then each data line to the simm slot. And finally troubleshoot /OE and /CE. The original ROM chips WERE working when I cut them off though.

Does anyone else want to have a look at the spec sheet and see if the boot block or lockout mode could be interfering? I can't completely rule that one out.

http://www.raphnet.net/electronique/genesis_cart/doc0998.pdf