I checked out the IIci Cache Card as my first line of inquiry and decided that puppy was waaay past figuring out, as expected. I remembered there was a big honking ASIC mounted dead center, but was surprised to see two different types of SRAM . . . WTH(eck) is "Tag SRAM," WTH does it do and W(ho)TH cares?
Whatever . . . the big honking ASIC's name is: NMC CONTROLLER, but its function is readily apparent . . .
. . . some sort of black magic having to do with cache cards . . . DUH!!
Checked out the DevNote specs for the DuoDock, no L2 Cache, drat! The ICs that I recalled were VRAM. The L2 Cache is in the Dock II and the Dock+ but I have a working Dock+ on hand to test it out. I finally found the DevNote for the DuoDock II . . . this appears to be about as complicated as I was figuring it might wind up being. FEH!
I didn't remember any specialized ASIC on my Dock+ board that might be for controlling Cache and I was right . . . Apple rolled the Cache Controller into the JET Video Controller along with the SWIM . . . %^!$@#%$#$^%!!!!!!!!
Maybe it's a lot more simple than the IIci Cache implementation . . . at least there's none of that freakin' TAG SRAM in the Spec! :
Does anyone remember seeing any documentation for adding Cache to the 68030? :?:
Whatever . . . the big honking ASIC's name is: NMC CONTROLLER, but its function is readily apparent . . .
. . . some sort of black magic having to do with cache cards . . . DUH!!
Checked out the DevNote specs for the DuoDock, no L2 Cache, drat! The ICs that I recalled were VRAM. The L2 Cache is in the Dock II and the Dock+ but I have a working Dock+ on hand to test it out. I finally found the DevNote for the DuoDock II . . . this appears to be about as complicated as I was figuring it might wind up being. FEH!
I didn't remember any specialized ASIC on my Dock+ board that might be for controlling Cache and I was right . . . Apple rolled the Cache Controller into the JET Video Controller along with the SWIM . . . %^!$@#%$#$^%!!!!!!!!
Maybe it's a lot more simple than the IIci Cache implementation . . . at least there's none of that freakin' TAG SRAM in the Spec! :
Does anyone remember seeing any documentation for adding Cache to the 68030? :?: