I would suggest reading the original Motorola data sheets for the 68k CPU family. I've looked at it a little and it sort of made my head hurt.

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I have been too, and ditto about the pain.

from skimming the manual it would in theory be possible to design a 68k computer which used up to *eight* separate 32 bit address spaces for different priority software and use the output of those function pins in any number of ways to enforce security.

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I noticed that too. It looks like with care, one could use the FC pins as the equivalent of address pins (except one must change modes to change them, instead of writing them into addresses explicitly) and actually have an address space of 32 GB in a 68030 machine. I think the MMU enforcing security restrictions might be inconvenient though.

The one succinct explanation I did see about the workings of those pins implied that normally they were used by the MMU and that the physical memory subsystem doesn't necessarily need to care about them. (IE, the MMU will do the job of comparing the function codes to the translation tables it maintains and allow or deny access at that level.)

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That was my reading as well, which is why I was puzzled that...

It *may* be that the only reason the 68030 has the pins brought out despite having a built-in MMU is to allow the chip to be used to upgrade older designs with proprietary memory management systems.

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That makes sense. I was having trouble imagining why, if the signals are really just relevant to the MMU, why are they on the external bus. For that matter, why are they in the PDS slot? But I guess putting them in the PDS slot allows third party developers to build security conscious add-ons or something.

Or we're both overlooking the same thing. I even went and dug around in the 68020 and 68851 datasheets for answers, but didn't get any different ones; in the 68020/68851 combination, the diagram of |Logical bus <--> 68851 <--> Physical bus| doesn't seem to propagate the FC pins to the physical bus side of the diagram, supporting our conclusions.

I wonder if this is addressed at all in "Inside Macintosh". Perhaps I'll skim through DCADFTM this weekend to see if it mentions the FC lines. Probably not, since it is oriented on NuBus and I don't believe that NuBus propagates the FC lines.

It makes a three pin difference in how many FPGA pins I need to interface with the PDS slot in the SE/30 and I'm hurting for pins. The FPGA I'm eyeing has 372 I/O pins, but the Xilinx Starter Kit with that chip on it, which I want to use, doesn't have very many unused pins readily available.

There are 43 in the 100 pin connector (huh?, why aren't there at least 50?). And there are three 6-pin headers where I can get four I/O pins each. And a couple of differential headers where I can grab another 24 total. So that's 43 + 12 + 24 = 79 and the Starter Kit is out of readily available pins.

Everything else is being used for expansion components built into the Starter Kit, or isn't brought out from the main chip. By my count, the Starter Kit board uses 283 I/O pins, so there should still be 89 pins available. I don't know why they didn't bring more of them out to usable connectors. Probably board routing issues, I guess.

A rough count of the PDS slot says I may need as many as 86 pins to interface properly. If I can ignore FC, that's down to 83, only four more to go!