Thanks guys. So I guess the FC signals are present in the PDS slot to support the possibility that someone would build a coprocessor board of some kind. That makes sense. And it also seems that I can ignore them.
Unless there's some situation where the FC pins would indicate a 68881 transaction, but the address pins would be indicating the address space my card is decoding.
Hmmm. Better go double check that...
Okay, I was starting to worry that I would have to decode the three FC lines in the FPGA, or at least set up a little external logic to create a sort of anti-chip select when FC = 111. However, in the MC68030UM, section 10, I found this:
I need to check some more details to confirm that there isn't some detail that will get me, but I think it's safe to ignore the FC lines.
Unless there's some situation where the FC pins would indicate a 68881 transaction, but the address pins would be indicating the address space my card is decoding.
Hmmm. Better go double check that...
Okay, I was starting to worry that I would have to decode the three FC lines in the FPGA, or at least set up a little external logic to create a sort of anti-chip select when FC = 111. However, in the MC68030UM, section 10, I found this:
Since the address space I'll be using are always going to have some non-zero value in bits A31-A30 or in A24-A23, I can decode just the address bus and be assured that I'm not interfering in a transaction which was meant for a coprocessor.
I need to check some more details to confirm that there isn't some detail that will get me, but I think it's safe to ignore the FC lines.