Right now I'm using the Spartan 3A FPGA starter kit from Xilinx. All the other "hardware" is actually synthesized inside the FPGA: a 68000 soft-CPU (TG68 core from opencores.org), 32K RAM, and 8K ROM. The synthetic RAM/ROM sizes are much too small, but are all that would fit inside the FPGA.

Click to expand...

Heh. If you had the Spartan 3AN Starter Kit, you'd have something like 700K of ROM available on board the FPGA.

Those block RAMs really don't add up to all that much RAM, do they?

If you want to use the DDR2, I would start with the demo that Xilinx has available. I don't know how hard that is to get up and running, but it seems like the logical starting point. Programming your own DDR2 controller would be a ridiculous amount of work.

And on the Starter Kit it's 16 bits wide, so the width is just what it should be. Gonna be a lot of wasted transactions, with the DDR2 insisting on doing 4 word bursts for every transaction though...

Maybe add connectors for vintage keyboard, mouse, serial, and even floppy if I can find a source for DB-19's!

Click to expand...

I posted a source in a new thread on this forum.

well with the JIT soft-core running on the FPGA

Click to expand...

It's actually not a JITter, but a full-fledged 68000 realized from the "sea of gates" of the FPGA. So there's no emulation or dynamic recompliation involved. It's basically exactly the same as having a real 68000, just internal to the FPGA.

Click to expand...

What is "JIT soft-core " and how does it differ from what you implemented.

Did someone run off with the designs from Motorola, or is the FPGA 68000 design reverse engineered from the 68000's behaviour?