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Home▸ Forums▸ 68kMLA▸ Plus Too: a DIY Mac clone project (128k -> Plus) — #23
Post #23 by Gorgonops
Source Forum68kMLA
CategoryHardware
Post DateWed, 14 Sep 2011 - 18:32
Original URLhttps://68kmla.org/bb/threads/plus-too-a-diy-mac-clone-project-128k-gt-plus.23753/
Post
What is "JIT soft-core " and how does it differ from what you implemented.
JIT = Just In Time (compilation). It's a method of speeding execution of interpreted languages (and emulators, since one CPU running code for another is broadly the same thing as running an interpreted language) by compiling snippets of code into native equivalents in psuedo-real (just in) time and caching the compiled version for later use when appropriate.

In the context of emulator software the word "core" could refer to the software component that emulates *any* part of the emulated system (like a chipset) but without modifiers usually means the CPU emulator. And many emulators allow the user to choose between several. Modern builds of BasiliskII on x86, for instance, generally have a "JIT core", which itself has several performance-enhancing options that can be turned on and off, alongside a much slower interpretive core which persists as an fallback in case one encounters a bug with the JIT core. (JIT cores are "hard", and tricks like self-modifying code can break them.)

"JIT Soft-Core" is thus meaningless in the context of an FPGA because an FPGA isn't a "CPU" with a native instruction set. It's basically a huge pile of electronic tinkertoys that can be interconnected according to a "meta-code", VHDL or Verilog, that has nothing to do with the normal operation of the chip once it's programmed. (Once the FPGA is programmed it's not "emulating" the chips it's coded for, it in essence *is* the chips.) An FPGA "core" is a collection of code that describes to the FPGA how to connect its tinkertoys to make a working copy of another chip, and for a given CPU or other IC there may be multiple "cores" floating around which incorporate different trade-offs. For instance, one core might uses less gates than another, thus leaving more space on the FPGA for other things, but the tradeoff may be that it can't be clocked as high. Another case may be that for a given CPU there exists a commercially licensed version which is "guaranteed" to perfectly replicate the real thing, unlike a free reverse-engineered open-source version.