I don't know much about the 68000's bus cycle (it's considerably more complicated than the 8 bit CPUs I semi-understand), but looking at the 68000 data sheet and how the 68000 is wired up in the Mac if I had to take a wild guess it may be possible to pause the CPU for at *least* one cycle using the /DTACK signal. (There's a section in the manual explaining how the 68000 can operate in either "synchronous" or "asynchronous" modes.) One thing they're not doing is using the multi-busmaster arbitration support, as it looks like all those lines are tied off, and HALT shows as being tied to RESET.

(That "schematic" really is pretty useless in some respects. It might help with troubleshooting a unit, but what you want to see is the *details* of the DRAM controller and any details on that are completely absent. Undoubtedly it's all tied up in the PALs.)

And... I just loaded the URL to your independently cooked-up design. I'm sort of an idiot but it looks good to me. ;^)

(I assume you're planning to simplify things and just use SRAM in your replica instead of bothering with DRAM?)