Sorry, by "buffer" I meant a bus driver, like a 74LS244 or '245.
As far as the seprate Din and Dout pins, I could be wrong here. I just googled the 4164 DRAM datasheet and looked at the pin configuration: http://www.speccy.org/hardware/datasheet/4164.pdf
You need a bus driver to isolate the CPU data bus from RAM output, so the CPU can read/write to peripherals or ROM without interference even while the RAM is outputting pixel data for the video circuitry. It should drive data from the RAM output to the CPU data bus only when the CPU is reading from RAM.
If RAM input and output are physically separate lines, as the above datasheet shows, then that's all you need. But if RAM has just a single "data" line that's used for both input and output, which is the case for all the SRAM I'm familiar with, then you'll also need a second bus driver working in the opposite direction, driving data from the CPU data bus to the RAM data lines. Without a bus driver working in that direction, when using SRAM and its single data line, there would be no way to to get data from the CPU into RAM.
A '245 bidirectional bus driver could meet both needs, but the Mac schematic shows it uses the unidirectional '244 instead, which is what leads me to believe the DRAM has separate data input and output lines.
EDIT: Looking at http://www.digibarn.com/collections/diagrams/mac-512klogicboard/mac-logic-schematic.jpg again, you can see the DRAMs at the bottom center, and they do in fact have separate D inputs and Q outputs.
As far as the seprate Din and Dout pins, I could be wrong here. I just googled the 4164 DRAM datasheet and looked at the pin configuration: http://www.speccy.org/hardware/datasheet/4164.pdf
You need a bus driver to isolate the CPU data bus from RAM output, so the CPU can read/write to peripherals or ROM without interference even while the RAM is outputting pixel data for the video circuitry. It should drive data from the RAM output to the CPU data bus only when the CPU is reading from RAM.
If RAM input and output are physically separate lines, as the above datasheet shows, then that's all you need. But if RAM has just a single "data" line that's used for both input and output, which is the case for all the SRAM I'm familiar with, then you'll also need a second bus driver working in the opposite direction, driving data from the CPU data bus to the RAM data lines. Without a bus driver working in that direction, when using SRAM and its single data line, there would be no way to to get data from the CPU into RAM.
A '245 bidirectional bus driver could meet both needs, but the Mac schematic shows it uses the unidirectional '244 instead, which is what leads me to believe the DRAM has separate data input and output lines.
EDIT: Looking at http://www.digibarn.com/collections/diagrams/mac-512klogicboard/mac-logic-schematic.jpg again, you can see the DRAMs at the bottom center, and they do in fact have separate D inputs and Q outputs.