In every "Universal" ROM (IIsi and up?), there is a table that contains information about specific machines the ROM knows about. This includes things like what address decoder it has, VIA initialization values, slot information, RAM bank sizing, onboard video setup, how to access PRAM, RTC, etc.
The Quadra 650's RAM setup information in this table indicates address space and probing for 64MB/socket.

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That is very cool. I'm looking forward to your ultimate results on this. As far as I can tell, 64MB and 128MB SIMMs use 12 column address bits and 12 row address bits (the 128MB SIMM has two banks).

So, given its behaviour, I surmise that the Q650 supports 12 address bits in the row or the column, but only supports 11 address bits in the other. Hence, it does 12 X 11 addressing, and 32 MB is the most that can be addressed in a bank. It must support two bank SIMMs, because common 32 MB SIMMs are actually two banks of 16MB, and because the 128MB SIMMs would have the same capacity as 64MB SIMMs if two banks were not supported.

Have you seen anything in there which seems to define the row and column addressing supported?