I was thinking the PDS connector necessitated at least 3 layers since there are 3 rows of pins close together, but the Asante card sneaks two lines between each pin, so if that clearance, tolerance and minimum feature size scheme is allowed by the fab-house, then I could see it done with a 2-layer board. There may be electrical reasons for needing more than two layers though, but that determination is out of my design space.

I don't see any reason why a 30-pin SIMM cannot be done with two layers without digging into details, but I think dougg3's ROM design shows it can be done.