I guess these old processors aren't pipelined at all?
So a simple memory access takes a cycle to fetch the instruction (if it's in cache and not in RAM) and a cycle to decode, and a cycle to put the address on the address bus and a cycle to receive or write the data, or something like that? And maybe more than one cycle to fetch the instruction if it's a multi-word instruction, perhaps with a 32 bit address embedded in it?
Is that close to how it's working?
I'm so used to thinking of a memory access taking one cycle these days, that I've always considered the SE/30 as having a theoretical bandwidth of 32 bits X 16 MHz = 64 MB/s. So wrong. Sigh.
So a simple memory access takes a cycle to fetch the instruction (if it's in cache and not in RAM) and a cycle to decode, and a cycle to put the address on the address bus and a cycle to receive or write the data, or something like that? And maybe more than one cycle to fetch the instruction if it's a multi-word instruction, perhaps with a 32 bit address embedded in it?
Is that close to how it's working?
I'm so used to thinking of a memory access taking one cycle these days, that I've always considered the SE/30 as having a theoretical bandwidth of 32 bits X 16 MHz = 64 MB/s. So wrong. Sigh.