Well if there isnt any open source SCSI files for FPGA, perhaps we can do the opposite.
There are Z80 systems for the FPGA. We can take the address decoding, the ROM/RAM/ETC and toss it all on the FPGA, as the libraries are already out there. just have to patch them all together, and map the external I/O to the SCSI IC, and the ATA port.
For simplicity though, once the Z80 project is complete, i guess for a start we could simply implement all the tie-in glue logic, 74 series logic into a CPLD to help reduce the IC count. I am thinking in terms of 2.5" compatibility. Get rid of the UART, and use the PLCC versions of the Z80 and firmware, and SMD RAM. As a start.
There are Z80 systems for the FPGA. We can take the address decoding, the ROM/RAM/ETC and toss it all on the FPGA, as the libraries are already out there. just have to patch them all together, and map the external I/O to the SCSI IC, and the ATA port.
For simplicity though, once the Z80 project is complete, i guess for a start we could simply implement all the tie-in glue logic, 74 series logic into a CPLD to help reduce the IC count. I am thinking in terms of 2.5" compatibility. Get rid of the UART, and use the PLCC versions of the Z80 and firmware, and SMD RAM. As a start.