Some semi-focus notes on the subject of peripherals:
The SE makes a pretty decent prototyping machine. It has a connector for ease of accessing the signals, it's slow, but most important, the entire 24bit address space is valid (the peripheral bus is only 24 address lines). For all Nubus and PDS slots, the official Slot address space is only mapped in if a valid declrom is found. Which kind of means you have to have the declrom present and correct before you can do any further hardware prototyping. There is space in the 030 PDS set aside for non-Slot Manager based cards (presumably accelerators), which should be mapped in with no declrom. But, one ease-of-use advantage the SE's 68000 bus has over the 030 PDS is the SE's memory controller will automatically acknowledge accesses, so you don't have to ack anything yourself.
It looks to me like you can just throw something on the SE's bus, particularly in the 0xE00000-0xFFFFFF range (it automatically generates /VPA or Valid Peripheral Address), key off of /AS (Address Strobe), decode the address to see if you should respond, and either respond or not. Looking at /RW as appropriate
68k takes 4 cycles to perform a read or a write operation. The SE is 8MHz. IMO, using TTL to do address decoding which goes to an interrupt on a microprocessor isn't completely crazy. The SE's data bus is 16bits wide. If you can put the address bits, data bits, and /RW into a single register of the microprocessor, so much the better since it can read all the relevant information with a single operation.
Anyway, just some thoughts.
The SE makes a pretty decent prototyping machine. It has a connector for ease of accessing the signals, it's slow, but most important, the entire 24bit address space is valid (the peripheral bus is only 24 address lines). For all Nubus and PDS slots, the official Slot address space is only mapped in if a valid declrom is found. Which kind of means you have to have the declrom present and correct before you can do any further hardware prototyping. There is space in the 030 PDS set aside for non-Slot Manager based cards (presumably accelerators), which should be mapped in with no declrom. But, one ease-of-use advantage the SE's 68000 bus has over the 030 PDS is the SE's memory controller will automatically acknowledge accesses, so you don't have to ack anything yourself.
It looks to me like you can just throw something on the SE's bus, particularly in the 0xE00000-0xFFFFFF range (it automatically generates /VPA or Valid Peripheral Address), key off of /AS (Address Strobe), decode the address to see if you should respond, and either respond or not. Looking at /RW as appropriate
68k takes 4 cycles to perform a read or a write operation. The SE is 8MHz. IMO, using TTL to do address decoding which goes to an interrupt on a microprocessor isn't completely crazy. The SE's data bus is 16bits wide. If you can put the address bits, data bits, and /RW into a single register of the microprocessor, so much the better since it can read all the relevant information with a single operation.
Anyway, just some thoughts.