dougg3: for the timing, this is my understanding:
The memory controller (GLUE/OSS/MDU/whatever) will terminate the bus read/write with a /BERR at the end of the 4th clock cycle (68k read/write operations take 4 cycles) if it hasn't already been terminated with a /DSACK{0,1} or /STERM or similar. I think. Another way to read it is /AS needs to be deasserted by the end of the 4th cycle, which potentially means slightly less time since the successful termination signals would need time to have been setup and handled. Which it is seems to vary by which part of which document you look at...
However, on the 680000 machines (possibly minus the Classic) won't timeout bus operations with an error, instead they will terminate them with success, and how exactly it is terminated depends on the address space being accessed. 0xE0000-0xFFFFFF generate /VPA or Valid Peripheral Address.
The 8MHz SE documents this as 265ns after /AS is asserted.
This also means your estimates are longer than you'd really have because /AS isn't asserted until the 2nd cycle of the operation.
I think we talked about microcontrollers being too slow in the other thread, which I completely agree with for the faster machines used by the ROM SIMM. My mention of them was specifically for the slower 68000 machines.
The memory controller (GLUE/OSS/MDU/whatever) will terminate the bus read/write with a /BERR at the end of the 4th clock cycle (68k read/write operations take 4 cycles) if it hasn't already been terminated with a /DSACK{0,1} or /STERM or similar. I think. Another way to read it is /AS needs to be deasserted by the end of the 4th cycle, which potentially means slightly less time since the successful termination signals would need time to have been setup and handled. Which it is seems to vary by which part of which document you look at...
However, on the 680000 machines (possibly minus the Classic) won't timeout bus operations with an error, instead they will terminate them with success, and how exactly it is terminated depends on the address space being accessed. 0xE0000-0xFFFFFF generate /VPA or Valid Peripheral Address.
The 8MHz SE documents this as 265ns after /AS is asserted.
This also means your estimates are longer than you'd really have because /AS isn't asserted until the 2nd cycle of the operation.
I think we talked about microcontrollers being too slow in the other thread, which I completely agree with for the faster machines used by the ROM SIMM. My mention of them was specifically for the slower 68000 machines.