using a microcontroller directly probably is too slow. Using a CPLD in between is probably the best approach to this, aside using an FPGA. If the CPLD is used, it could be setup to handle all the bus phases as required. then the CPU itself can just do whatever it wants with the data, whenever it wants, and take as long as it wants.

Stupid thought: What about using a logic analyzer on the bus? This way you could code an subroutine to just poke/peek an arbitrary address, the logic analyzer will pick it up and youll know exactly which signals have to be asserted when/how, For me it makes it clearer than trying to read a timing diagram in a 68K Doc.

speaking of Docs, I did find this:

http://courses.cs.tamu.edu/cpsc462/walker/Slides/68K_Timing_Diagrams.pdf

That help?