Honestly... I sort of have to respect what they did here. Clearly they were on a mission to make a Color Macintosh as cheaply as possible and they pretty much pulled no punches doing it. Or, to put it another way, it comes by its cheapness "honestly" rather than just being a better machine trivially kneecapped. There are advantages to the way they did it; by limiting system RAM to 10MB they removed the need to remap memory out of the 24 bit addressing area, which meant the 68020's lack of an MMU was no problem. (And the resulting chipset could be simpler than the HMMU they stuck in the original MMU-socketed-Mac II.) In fact, the architecture is so "16 bit-y" I have to wonder if they might have given thought to basing it on the 68000 and only discarded the idea because they didn't want to encourage authors to write non-32-bit-clean color software. (Or maintain a 68000 version of Color Quickdraw.)
Of course, a downside of using a downsized bus for RAM means that not only is the bus half as wide, it has to run in asynchronous mode. (IE, you can't use the synchronous or burst modes supported by the 68030.) That makes it a minimum of three clock cycles per bus transfer, vs. the two of a machine that can use synchronous mode, *plus* needing at least two bus cycles to read a 32 bit word. (Three if it's not word-aligned, although that probably wasn't a huge problem most of the time because the 68000 requires at least instructions to be aligned to even addresses; that restriction was lifted with the 68020 but violating it entails a speed penalty.) So compared to, say, a "real" 68030 Mac like the IIfx, a typical instruction read takes at least six clock cycles verses two. Ouch. But hey, it's honestly cheap!
Oh, another thing that sort of torpedoes this "make it wider" idea: The memory controller also has the sound generation hardware embedded in it and that uses 16 bit DMA. There's basically no way you're going to be able to patch that up externally.
Of course, a downside of using a downsized bus for RAM means that not only is the bus half as wide, it has to run in asynchronous mode. (IE, you can't use the synchronous or burst modes supported by the 68030.) That makes it a minimum of three clock cycles per bus transfer, vs. the two of a machine that can use synchronous mode, *plus* needing at least two bus cycles to read a 32 bit word. (Three if it's not word-aligned, although that probably wasn't a huge problem most of the time because the 68000 requires at least instructions to be aligned to even addresses; that restriction was lifted with the 68020 but violating it entails a speed penalty.) So compared to, say, a "real" 68030 Mac like the IIfx, a typical instruction read takes at least six clock cycles verses two. Ouch. But hey, it's honestly cheap!
Oh, another thing that sort of torpedoes this "make it wider" idea: The memory controller also has the sound generation hardware embedded in it and that uses 16 bit DMA. There's basically no way you're going to be able to patch that up externally.