Dunno, my working assumption on the matter is that there's little but a crystal, an FPU socket and the CPU on the card. There's nothing like the complexity of the Mobius 030 on that .jp page to get in the way of it working in a relatively plug-n-play scenario.
My gut tells me this accelerator just sits on the 68000 bus and bangs the crap out of it as fast as it can to get the maximum performance increase possible. It may have half as much time to latch the signals that it bangs out of the Portable's I/O bus, but it doesn't necessarily NEED the other half of the latch window that underclocking the system bus would provide.
At 8-16MHz we're still talking a low speed, unified bus system. The Mac didn't switch to the High/Low speed dual I/O bus model until about the time CPUs passed by the 25-33MHz barrier, IIRC. The first instance of an asynchronous I/O bus was probably the half-speed PDS of the IIfx. That was more likely due to the limits of 1989 PCB technology and RFI considerations than electrical necessity. The 840AV, with a full 68040 at the same clock rate has a unified I/O bus and a full speed PDS.
IIRC, asynchronous I/O first appeared in general on the Mac as an on die feature in the last series of "clock doubled" 68k CPUs. Dual I/O buses, clock multipliers and resistor blocks came much later to the Mac MoBo, when PPC CPUs doubled and tripled the 25-33MHz I/O barrier's limitations.
Maybe it'll work, maybe it won't. At this point it's all inference and WAG time.
If I do manage to stick with the project and get really lucky, we'll see, who knows? ;D
My gut tells me this accelerator just sits on the 68000 bus and bangs the crap out of it as fast as it can to get the maximum performance increase possible. It may have half as much time to latch the signals that it bangs out of the Portable's I/O bus, but it doesn't necessarily NEED the other half of the latch window that underclocking the system bus would provide.
At 8-16MHz we're still talking a low speed, unified bus system. The Mac didn't switch to the High/Low speed dual I/O bus model until about the time CPUs passed by the 25-33MHz barrier, IIRC. The first instance of an asynchronous I/O bus was probably the half-speed PDS of the IIfx. That was more likely due to the limits of 1989 PCB technology and RFI considerations than electrical necessity. The 840AV, with a full 68040 at the same clock rate has a unified I/O bus and a full speed PDS.
IIRC, asynchronous I/O first appeared in general on the Mac as an on die feature in the last series of "clock doubled" 68k CPUs. Dual I/O buses, clock multipliers and resistor blocks came much later to the Mac MoBo, when PPC CPUs doubled and tripled the 25-33MHz I/O barrier's limitations.
Maybe it'll work, maybe it won't. At this point it's all inference and WAG time.
If I do manage to stick with the project and get really lucky, we'll see, who knows? ;D