That chip U1 is the decode logic specifically for allocating the cache correctly on the databus, as the cache isnt using nubus space. its more memory mapped
Post #59 by techknight
| Source Forum | 68kMLA |
|---|---|
| Category | 68k |
| Post Date | Mon, 6 Jan 2014 - 05:16 |
| Original URL | https://68kmla.org/bb/threads/techknighttm-lc-pds-network-card-in-a-se-30.29478/ |
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