If you've got some wire wrap wire, you're good for the jumper tests.
Sounds like if you interconnect the ROW Address Select lines between the Soldered "Bank" and the SIMM "Bank" properly, you might see all 8MB of the soldered replacement RAM. If certain RAS lines are omitted on either end, those Rows of your Chips a/o SIMMs aren't addressable, hence, invisible!
Dunno, just a WAG on my part, but it's sounding more likely from I can parse in your report. Try setting up a block diagram of the LC memory setup on paper.
Have you searched for the DevNote?
ARRRGH!!!!!
Been there, done that, is the LC DevNote still MIA gang? :?:
Sounds like if you interconnect the ROW Address Select lines between the Soldered "Bank" and the SIMM "Bank" properly, you might see all 8MB of the soldered replacement RAM. If certain RAS lines are omitted on either end, those Rows of your Chips a/o SIMMs aren't addressable, hence, invisible!
Dunno, just a WAG on my part, but it's sounding more likely from I can parse in your report. Try setting up a block diagram of the LC memory setup on paper.
Have you searched for the DevNote?
ARRRGH!!!!!