Yep, using the control lines I can access just the necessary sections of each 72-pin SIMM needed to output the 8bits of needed to make the 32bit word in each access far Banks A & B . . .
. . . figuring out how the Data and Addressing is multiplexed(?) in the four 74ALS275 3-State Bus Transceivers should be a big help . . .
. . . or a major hindrance! ;D
It looks like I need to reflect the Control, Data and Address lines of Bank A back onto the bus for Bank B and find or synthesize a Bank Select in order to make this work. I'm hoping I can manage to do that on the two n.c. pins of the 30-pin SIMMs/Slots, dunno, we'll see. Worst case scenario for that appears to be the need to put a circuit on a PCB somewhere between MDU and Bank A to make a gate circuit on my 30-pin to 72-pin adapters work as planned.
Gotta love playing with a 20-33MHz memory bus! :
This thread was a false alarm, I forgot about the SE/30 and IIci using MDU for full A & B SIMM bankage. All the lines are there, with just resistor packs between them and the Bank B SIMMs/Bank A DRAM ICs.
The killer is that I don't really have any need to do this hack, the Rocket, its onboard memory banks and its Fast SCSI II storage subsystem will be the main CPU and I/O in the SuperIIsi under RocketShare. This hack is really just for fun!
. . . figuring out how the Data and Addressing is multiplexed(?) in the four 74ALS275 3-State Bus Transceivers should be a big help . . .
. . . or a major hindrance! ;D
It looks like I need to reflect the Control, Data and Address lines of Bank A back onto the bus for Bank B and find or synthesize a Bank Select in order to make this work. I'm hoping I can manage to do that on the two n.c. pins of the 30-pin SIMMs/Slots, dunno, we'll see. Worst case scenario for that appears to be the need to put a circuit on a PCB somewhere between MDU and Bank A to make a gate circuit on my 30-pin to 72-pin adapters work as planned.
Gotta love playing with a 20-33MHz memory bus! :
This thread was a false alarm, I forgot about the SE/30 and IIci using MDU for full A & B SIMM bankage. All the lines are there, with just resistor packs between them and the Bank B SIMMs/Bank A DRAM ICs.
The killer is that I don't really have any need to do this hack, the Rocket, its onboard memory banks and its Fast SCSI II storage subsystem will be the main CPU and I/O in the SuperIIsi under RocketShare. This hack is really just for fun!